发明授权
- 专利标题: Geometric D/A converter for a delay-locked loop
- 专利标题(中): 用于延迟锁定环路的几何D / A转换器
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申请号: US10986707申请日: 2004-11-12
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公开(公告)号: US06975260B1公开(公告)日: 2005-12-13
- 发明人: Shahram Abdollahi-Alibeik , Chaofeng Huang
- 申请人: Shahram Abdollahi-Alibeik , Chaofeng Huang
- 申请人地址: US CA San Jose
- 专利权人: T-RAM, Inc.
- 当前专利权人: T-RAM, Inc.
- 当前专利权人地址: US CA San Jose
- 主分类号: H03M1/66
- IPC分类号: H03M1/66 ; H03M1/68 ; H03M1/74
摘要:
A geometric DAC architecture includes a series of substantially identical sub-DACs, each sub-DAC having n taps. The sub-DACs are fed from a bias-DAC having m=(total number of taps needed)/n taps. The output of each of the m taps is increased geometrically at a rate of kn. The geometric DAC architecture control lines desirably require only (m+n) taps compared with (m×n) taps for the simpler more conventional approach. Further, the geometric DAC architecture requires less real estate than the simpler more conventional approach, is easy to expand because it is modular, and generates an output current that is always monotonic, regardless of errors in transistor sizes and PVT variations. The n tap control lines are coded by alternately inverting n control line inputs between sub-DACs such that any state transition associated with the geometric DAC occurs with only one bit change in each of the control lines.