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公开(公告)号：US06734815B1
公开(公告)日：2004-05-11
申请号：US10396884
申请日：2003-03-25
IPC分类号： H03M166
摘要： A geometric DAC architecture includes a series of substantially identical sub-DACs, each sub-DAC having n taps. The sub-DACs are fed from a bias-DAC having m=(total number of taps needed)/n taps. The output of each of the m taps is increased geometrically at a rate of kn. The geometric DAC architecture control lines desirably require only (m+n) taps compared with (m×n) taps for the simpler more conventional approach. Further, the geometric DAC architecture requires less real estate than the simpler more conventional approach, is easy to expand because it is modular, and generates an output current that is always monotonic, regardless of errors in transistor sizes and PVT variations. The n tap control lines are coded by alternately inverting n control line inputs between sub-DACs such that any state transition associated with the geometric DAC occurs with only one bit change in each of the control lines.
摘要翻译： 几何DAC架构包括一系列基本相同的子DAC，每个子DAC具有n个抽头。 子DAC从具有m =（所需抽头总数）/ n抽头的偏置DAC馈送。 每个m个抽头的输出以k
的速率几何地增加。 对于更简单的更传统的方法，几何DAC架构控制线期望仅需要（m + n）个抽头与（m×n）抽头相比较。 此外，几何DAC架构比简单的更传统的方法需要更少的空间，由于它是模块化而容易扩展，并且产生总是单调的输出电流，而不管晶体管尺寸和PVT变化中的错误。 通过在子DAC之间交替地反转n个控制线输入来编码n个抽头控制线，使得与几何DAC相关联的任何状态转换在每个控制线中仅发生一个位改变。 -
公开(公告)号：US06975260B1
公开(公告)日：2005-12-13
申请号：US10986707
申请日：2004-11-12
摘要： A geometric DAC architecture includes a series of substantially identical sub-DACs, each sub-DAC having n taps. The sub-DACs are fed from a bias-DAC having m=(total number of taps needed)/n taps. The output of each of the m taps is increased geometrically at a rate of kn. The geometric DAC architecture control lines desirably require only (m+n) taps compared with (m×n) taps for the simpler more conventional approach. Further, the geometric DAC architecture requires less real estate than the simpler more conventional approach, is easy to expand because it is modular, and generates an output current that is always monotonic, regardless of errors in transistor sizes and PVT variations. The n tap control lines are coded by alternately inverting n control line inputs between sub-DACs such that any state transition associated with the geometric DAC occurs with only one bit change in each of the control lines.
摘要翻译： 几何DAC架构包括一系列基本相同的子DAC，每个子DAC具有n个抽头。 子DAC从具有m =（所需抽头总数）/ n抽头的偏置DAC馈送。 m个抽头中的每一个的输出以几何的方式以k
的速率增加。 对于更简单的更传统的方法，几何DAC架构控制线期望仅需要（m + n）个抽头与（m×n）抽头相比较。 此外，几何DAC架构比简单的更传统的方法需要更少的空间，由于它是模块化而容易扩展，并且产生总是单调的输出电流，而不管晶体管尺寸和PVT变化中的错误。 通过在子DAC之间交替地反转n个控制线输入来编码n个抽头控制线，使得与几何DAC相关联的任何状态转换在每个控制线中仅发生一个位改变。 -
3.发明授权Apparatus and method for producing an output clock pulse and output clock generator using same 失效用于产生输出时钟脉冲和使用其的输出时钟发生器的装置和方法公开(公告)号：US06947349B1
公开(公告)日：2005-09-20
申请号：US10654258
申请日：2003-09-03
IPC分类号： G11C8/00 , G11C11/419 , G11C29/02
CPC分类号： G11C29/12015 , G11C11/41 , G11C11/419 , G11C29/02 , G11C29/028 , G11C29/1201 , G11C29/50012
摘要： A method and apparatus generates output clock pulses, having leading and trailing edges that are adjusted in a pulse forming processor, according to the relative phase of an output clock and output data. Dynamic adjustment of the leading and trailing edges of output clock pulses improves the performance of high-speed devices significantly.
摘要翻译： 一种方法和装置根据输出时钟和输出数据的相对相位产生具有在脉冲形成处理器中调整的前沿和后沿的输出时钟脉冲。 输出时钟脉冲的前沿和后沿的动态调整显着提高了高速器件的性能。
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4.发明授权Apparatus and method for producing dummy data and output clock generator using same 失效用于产生伪数据的装置和方法以及使用其的输出时钟发生器公开(公告)号：US07464282B1
公开(公告)日：2008-12-09
申请号：US10654322
申请日：2003-09-03
IPC分类号： G06F1/12
CPC分类号： G11C7/22 , G11C7/222 , G11C2207/2254 , H03L7/0814
摘要： An apparatus and method for producing dummy data is based on timing paths co-located with the address/data paths of the memory. An output clock generator uses the dummy data. The technique for producing dummy data is particularly important for memory systems in which the output of memory cells do not normally provide large voltage swings, making them less practical for self timing approaches to dummy data generation.
摘要翻译： 用于产生伪数据的装置和方法基于与存储器的地址/数据路径共同定位的定时路径。 输出时钟发生器使用虚拟数据。 用于产生虚拟数据的技术对于其中存储器单元的输出通常不提供大的电压摆动的存储器系统是特别重要的，使得它们对于伪数据生成的自定时方法不太实用。
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5.发明授权Architecture and method for output clock generation on a high speed memory device 失效用于在高速存储器件上产生输出时钟的架构和方法公开(公告)号：US07089439B1
公开(公告)日：2006-08-08
申请号：US10654358
申请日：2003-09-03
IPC分类号： G06F1/12
CPC分类号： G06F1/10
摘要： An output clock for a memory device having a read latency more than one clock cycle includes a clock generator at a central location on the device. A clock channel couples the clock generator to output structures. A timing path emulates the address/data paths in the memory, and is responsive to an address emulation signal produced by the clock generator to provide dummy data near the output structures. An output clock signal with an adjustable phase and a dummy data reference clock signal on the input of the clock channel are generated. A phase detector near the output structures, determines whether the output clock is early, late or on time with respect to the dummy data. Logic signals are produced at the phase detector, and returned to the clock generator for adjusting the relative phase of the output clock signal.
摘要翻译： 具有超过一个时钟周期的读等待时间的存储器件的输出时钟包括在器件上的中心位置处的时钟发生器。 时钟信道将时钟发生器耦合到输出结构。 定时路径模拟存储器中的地址/数据路径，并且响应于由时钟发生器产生的地址仿真信号，以在输出结构附近提供伪数据。 产生在时钟通道的输入端具有可调节相位和伪数据参考时钟信号的输出时钟信号。 在输出结构附近的相位检测器确定输出时钟是否相对于虚拟数据的早，晚或准时。 逻辑信号在相位检测器处产生，并返回到时钟发生器，用于调节输出时钟信号的相对相位。
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公开(公告)号：US06891774B1
公开(公告)日：2005-05-10
申请号：US10654561
申请日：2003-09-03
CPC分类号： G11C7/22 , G11C7/222 , G11C11/419 , G11C29/02 , G11C29/028 , G11C29/50012 , H03K5/133 , H03K2005/00032 , H03L7/0812
摘要： A delay line for an adjustable, high speed clock generator is based on two-stage multiplexing, in which for all pairs of adjacent taps, a change from a current tap to an adjacent tap in the pair is executed by switching only one of the first stage and second stage multiplexers. Control signals are generated for the first and second stage multiplexers by logic based on bidirectional shift registers. The delay line is suitable for generation of an output clock having an adjustable phase, allowing for smooth, glitch-free adjustment over a large range of phases.
摘要翻译： 用于可调节的高速时钟发生器的延迟线基于两级复用，其中对于所有相邻抽头对，通过仅切换第一级中的一个来执行从该对中的当前抽头到相邻抽头的改变 阶段和第二阶段多路复用器。 通过基于双向移位寄存器的逻辑为第一和第二级多路复用器产生控制信号。 延迟线适用于产生具有可调节相位的输出时钟，允许在大范围的相位上平滑，无故障地调整。
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公开(公告)号：US06819278B1
公开(公告)日：2004-11-16
申请号：US10808148
申请日：2004-03-24
IPC分类号： H03M166
摘要： A geometric DAC architecture includes a series of substantially identical sub-DACs, each sub-DAC having n taps. The sub-DACs are fed from a bias-DAC having m=(total number of taps needed)/n taps. The output of each of the m taps is increased geometrically at a rate of kn. The geometric DAC architecture control lines desirably require only (m+n) taps compared with (m×n) taps for the simpler more conventional approach. Further, the geometric DAC architecture requires less real estate than the simpler more conventional approach, is easy to expand because it is modular, and generates an output current that is always monotonic, regardless of errors in transistor sizes and PVT variations. The n tap control lines are coded by alternately inverting n control line inputs between sub-DACs such that any state transition associated with the geometric DAC occurs with only one bit change in each of the control lines.
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公开(公告)号：US08547169B2
公开(公告)日：2013-10-01
申请号：US13104899
申请日：2011-05-10
IPC分类号： H03K5/00
CPC分类号： H03H7/0153 , H03K5/24
摘要： A system and method are disclosed for reducing the kickback disturbance in an electronic circuit. The system is based on the coupling of a programmable noise filter between bias blocks. In one embodiment the programmable noise filter includes capacitors, resisters and switches and forms a C-R-C circuit structure. By selecting the resistance and capacitance values and the status of the switches, the performance of the programmable noise filter is determined. Also disclosed is a system and method to reduce kickback disturbances comprising N+1 bias blocks, N programmable noise filters, and a bias reference generator, wherein N is equal to or greater than one.
摘要翻译： 公开了一种用于减小电子电路中的反冲扰的系统和方法。 该系统基于偏置块之间的可编程噪声滤波器的耦合。 在一个实施例中，可编程噪声滤波器包括电容器，电阻器和开关，并形成C-R-C电路结构。 通过选择电阻和电容值以及开关的状态，确定可编程噪声滤波器的性能。 还公开了一种减少包括N + 1个偏置块，N个可编程噪声滤波器和偏置参考发生器的反冲扰的系统和方法，其中N等于或大于1。
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公开(公告)号：US08295845B1
公开(公告)日：2012-10-23
申请号：US12328128
申请日：2008-12-04
IPC分类号： H04W40/10
摘要： A calibration mechanism is disclosed for performing I/Q mismatch calibration operations in a wireless communication device comprising a receiver unit and a transmitter unit. During an I/Q mismatch calibration mode, a first signal and a second signal are provided from the transmitter unit to the receiver unit via a loopback path coupled between the transmitter and receiver units. A phase shift is added to the second signal that is provided to the receiver unit. A first set of I/Q measurements is determined from the first signal and a second set of I/Q measurements is determined from the second signal with the added phase shift. Transmitter and receiver I/Q mismatch parameters are calculated based on the first and second sets of I/Q measurements. The receiver and transceiver I/Q mismatch parameters are used to compensate for I/Q mismatch at the receiver and transmitter units, respectively.
摘要翻译： 公开了一种用于在包括接收器单元和发射器单元的无线通信设备中执行I / Q失配校准操作的校准机构。 在I / Q不匹配校准模式期间，经由耦合在发射机和接收机单元之间的环回路径，从发射机单元向接收机单元提供第一信号和第二信号。 将相移添加到提供给接收器单元的第二信号。 从第一信号确定第一组I / Q测量，并且从具有相加相移的第二信号确定第二组I / Q测量。 基于I / Q测量的第一组和第二组来计算发射机和接收机I / Q失配参数。 接收机和收发器I / Q失配参数分别用于补偿接收机和发射机单元的I / Q失配。
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公开(公告)号：US06941417B1
公开(公告)日：2005-09-06
申请号：US10017676
申请日：2001-12-14
CPC分类号： G11C15/00
摘要： The disclosed invention presents a method and apparatus to a one dimensional prefix search problem. The problem consists looking up the best match to a word out of a table of one-dimensional prefixes. The invention addresses the problems with prior art of high power consumption, large silicon chip area for implementation and slow search speed. The prefix entries are divided in several subgroups. A function is described that can be efficiently implemented to determine which of these subgroups the presented word will find a best match in. Thus, it is necessary to search only this small subgroup of prefixes. This saves on power consumption as well as area. An efficient hardware embodiment of this idea which can search at a very high speed is also presented. The applications for this invention could include internet routing, telephone call routing and string matching.
摘要翻译： 所公开的发明提供了一维前缀搜索问题的方法和装置。 这个问题包括从一维前缀的表中查找一个单词的最佳匹配。 本发明解决了高功耗现有技术的问题，实现的大芯片面积和搜索速度慢。 前缀条目分为几个子组。 描述了可以有效地实现的功能，以确定所呈现的单词中哪个子组将找到最佳匹配。因此，仅需要搜索该小子组的前缀。 这节省了功耗以及面积。 还提出了可以以非常高的速度搜索的这种想法的高效硬件实施例。 本发明的应用可以包括互联网路由，电话呼叫路由和字符串匹配。
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