Flash memory devices include at least one flash memory array and an address compare circuit that is configured to indicate whether an applied row address associated with a first operation (e.g., program, erase) is within or without an unlock area of the at least one flash memory array. A control circuit is also provided. This control circuit is configured to block performance of the first operation on the flash memory array in response to detecting an indication from the address compare circuit that the applied row address is outside the unlock area of the flash memory array.