Invention Grant
- Patent Title: Overlay error model, sampling strategy and associated equipment for implementation
- Patent Title (中): 覆盖误差模型，采样策略和相关设备实施
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Application No.: US09920034Application Date: 2001-08-01
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Publication No.: US06975974B2Publication Date: 2005-12-13
- Inventor: Chen-Fu Chien , Kuo-Hao Chang , Chih-Ping Chen , Shun-Li Lin
- Applicant: Chen-Fu Chien , Kuo-Hao Chang , Chih-Ping Chen , Shun-Li Lin
- Applicant Address: TW Hsinchu
- Assignee: Macronix International Co., Ltd.
- Current Assignee: Macronix International Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: J. C. Patents
- Priority: TW90104309A 20010226
- Main IPC: G03F7/20
- IPC: G03F7/20 ; H01L21/66 ; G06F17/10
Abstract:
In the manufacturing of VLSI circuits, production of overlay is a critical step. To obtain a higher resolution and alignment accuracy in microlithographic process, overlay errors must be measured so that overlay errors can be reduced to a tolerable level. This invention provides an overlay error model and a sampling strategy. Utilizing the overlay model and sampling strategy, a device for measuring overlay errors is also designed.
Public/Granted literature
- US20020183989A1 Overlay error model, sampling strategy and associated equipment for implementation Public/Granted day:2002-12-05
Information query
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