发明授权
US06975976B1 Property specific testbench generation framework for circuit design validation by guided simulation
失效
通过引导模拟进行电路设计验证的属性特定测试平台生成框架
- 专利标题: Property specific testbench generation framework for circuit design validation by guided simulation
- 专利标题(中): 通过引导模拟进行电路设计验证的属性特定测试平台生成框架
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申请号: US09693976申请日: 2000-10-23
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公开(公告)号: US06975976B1公开(公告)日: 2005-12-13
- 发明人: Albert E. Casavant , Aarti Gupta , Pranav Ashar
- 申请人: Albert E. Casavant , Aarti Gupta , Pranav Ashar
- 申请人地址: JP Tokyo
- 专利权人: NEC Corporation
- 当前专利权人: NEC Corporation
- 当前专利权人地址: JP Tokyo
- 代理机构: Sughrue Mion, PLLC
- 主分类号: G01R31/28
- IPC分类号: G01R31/28 ; G01R31/3183 ; G06F17/50
摘要:
Simulation continues to be the primary technique for functional validation of designs. It is important that simulation vectors be effective in targeting the types of bugs designers expect to find rather than some generic coverage metrics. The focus of this work is to generate property-specific testbenches that are targeted either at proving the correctness of a property or at finding a bug. It is based on performing property-specific analysis on iteratively less abstract models of the design in order to obtain interesting paths in the form of a Witness Graph, which is then targeted during simulation of the entire design. This testbench generation framework will form an integral part of a comprehensive verification system currently being developed.
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