发明授权
US06977879B1 Apparatus for adjusting phase of clock signal based on phase error calculated from sampled values of readout signal
失效
用于基于从读出信号的采样值计算的相位误差来调整时钟信号的相位的装置
- 专利标题: Apparatus for adjusting phase of clock signal based on phase error calculated from sampled values of readout signal
- 专利标题(中): 用于基于从读出信号的采样值计算的相位误差来调整时钟信号的相位的装置
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申请号: US09656692申请日: 2000-09-07
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公开(公告)号: US06977879B1公开(公告)日: 2005-12-20
- 发明人: Kenichi Hamada , Satoshi Furuta , Masakazu Taguchi
- 申请人: Kenichi Hamada , Satoshi Furuta , Masakazu Taguchi
- 申请人地址: JP Kawasaki
- 专利权人: Fujitsu Limited
- 当前专利权人: Fujitsu Limited
- 当前专利权人地址: JP Kawasaki
- 代理机构: Greer, Burns & Crain, LTD
- 优先权: JP11-361550 19991220
- 主分类号: G11B20/14
- IPC分类号: G11B20/14 ; G11B20/10 ; H04L7/027 ; G11B20/18
摘要:
A clock adjustment apparatus for adjusting a phase of a clock signal based on a phase error thereof is provided in a data reproduction system which samples a readout signal from a recording medium in synchronism with the clock signal, and reproduces data in accordance with a Viterbi algorithm by using sampled values of the readout signal. The recording medium is recorded with the data modulated in accordance with a recording rule of a predetermined partial response characteristic. The clock adjustment apparatus includes a phase error calculation circuit which calculates the phase error of the clock signal based on the sampled values of the readout signal.
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