发明授权
US06981131B2 Early condition code evaluation at pipeline stages generating pass signals for controlling coprocessor pipeline executing same conditional instruction
有权
在管线阶段的早期条件代码评估产生用于控制协处理器流水线执行相同条件指令的通过信号
- 专利标题： Early condition code evaluation at pipeline stages generating pass signals for controlling coprocessor pipeline executing same conditional instruction
- 专利标题（中）： 在管线阶段的早期条件代码评估产生用于控制协处理器流水线执行相同条件指令的通过信号
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申请号： US10233609申请日： 2002-09-04
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公开(公告)号： US06981131B2公开(公告)日： 2005-12-27
- 发明人: Ian Victor Devereux
- 申请人： Ian Victor Devereux
- 申请人地址： GB Cambridge
- 专利权人： ARM Limited
- 当前专利权人： ARM Limited
- 当前专利权人地址： GB Cambridge
- 代理机构： Nixon & Vanderhye P.C.
- 主分类号： G06F9/00
- IPC分类号： G06F9/00 ; G06F9/32 ; G06F9/38
摘要：
The present invention provides a data processing apparatus and method for evaluating condition codes comprising a pipelined processor operable to execute a sequence of instructions, a set of condition codes being maintained by the processor, and the state of the condition codes being set by execution of condition code setting instructions in the sequence. The sequence of instructions further includes conditional instructions that are conditionally executed depending on the state of a number of those condition codes, with the pipelined processor comprising a plurality of pipeline stages including a predetermined pipeline stage at which the state of the condition codes are set by the condition code setting instructions. Condition code evaluation logic is associated with the predetermined pipeline stage and is operable, when one of the conditional instructions is in the predetermined pipeline stage, to evaluate the state of the number of the condition codes in order to generate a pass signal indicating whether the conditional instruction is to be executed. Additional condition code evaluation logic is associated with a preceding pipeline stage, and is operable, when one of the conditional instructions is in that preceding pipeline stage, to evaluate the state of the number of the condition codes in order to generate an additional pass signal. Condition code setting instruction determination logic is operable to determine whether there is a condition code setting instruction in either the predetermined pipeline stage or any pipeline stages between said preceding pipeline stage and the predetermined pipeline stage.
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