发明授权
US06988184B2 Dyadic DSP instruction predecode signal selective multiplexing data from input buses to first and second plurality of functional blocks to execute main and sub operations
失效
Dyadic DSP指令预编码信号从输入总线选择性地复用数据到第一和第二多个功能块以执行主和次操作
- 专利标题: Dyadic DSP instruction predecode signal selective multiplexing data from input buses to first and second plurality of functional blocks to execute main and sub operations
- 专利标题(中): Dyadic DSP指令预编码信号从输入总线选择性地复用数据到第一和第二多个功能块以执行主和次操作
-
申请号: US10211387申请日: 2002-08-02
-
公开(公告)号: US06988184B2公开(公告)日: 2006-01-17
- 发明人: Kumar Ganapathy , Ruban Kanapathipillai
- 申请人: Kumar Ganapathy , Ruban Kanapathipillai
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Blakely, Sokoloff, Taylor & Zafman LLP
- 主分类号: G06F9/302
- IPC分类号: G06F9/302
摘要:
Methods of performing dyadic digital signal processing (DSP) instructions. In one embodiment of the invention, the method includes fetching a dyadic DSP instruction having a main operation and a sub operation; predecoding the dyadic DSP instruction to generate predecoded instruction signals; and decoding the predecoded instruction signals to generate select signals to selectively couple data from a first plurality of buses coupled to inputs of multiplexers of a first plurality of DSP functional blocks to execute the main operation of the dyadic DSP instruction in one processor cycle and to selectively couple data from a second plurality of buses coupled to inputs of multiplexers of a second plurality of DSP functional blocks to execute the sub operation of the dyadic DSP instruction in the one processor cycle.
公开/授权文献
- US20030018881A1 Methods of dyadic DSP instruction operation 公开/授权日:2003-01-23
信息查询