Invention Grant
US06989309B2 High voltage MOS transistor with up-retro well by providing dopant in an epitaxial layer
有权
高电压MOS晶体管通过在外延层中提供掺杂剂而具有良好的逆变性
- Patent Title: High voltage MOS transistor with up-retro well by providing dopant in an epitaxial layer
- Patent Title (中): 高电压MOS晶体管通过在外延层中提供掺杂剂而具有良好的逆变性
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Application No.: US10858619Application Date: 2004-06-01
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Publication No.: US06989309B2Publication Date: 2006-01-24
- Inventor: Francois Hebert
- Applicant: Francois Hebert
- Applicant Address: US CA Milpitas
- Assignee: Linear Technology Corporation
- Current Assignee: Linear Technology Corporation
- Current Assignee Address: US CA Milpitas
- Agency: Fish & Neave LP Group of Ropes & Gray LLP
- Agent Robert W. Morris; Jeffrey D. Mullen
- Main IPC: H01L31/113
- IPC: H01L31/113

Abstract:
A high voltage MOS transistor is provided that is compatible with low-voltage, sub-micron CMOS and BiCMOS processes. The high voltage transistor of the present invention has dopants that are implanted into the substrate prior to formation of the epitaxial layer. The implanted dopants diffuse into the epitaxial layer from the substrate during the formation of the epitaxial layer and subsequent heating steps. The implanted dopants increase the doping concentration in a lower portion of the epitaxial layer. The implanted dopants may diffuse father into the epitaxial layer than dopants in the buried layer forming an up-retro well that prevents vertical punch-through at high operating voltages for thin epitaxial layers. Particularly, a P-type dopant may diffuse farther up into an epitaxial layer than an N-type dopant to form an up-retro well.
Public/Granted literature
- US20040224472A1 High voltage MOS transistor with up-retro well Public/Granted day:2004-11-11
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