发明授权
US06989586B2 Integrated circuit packages with reduced stress on die and associated substrates, assemblies, and systems
失效
集成电路封装,在裸片和相关的基板,组件和系统上具有降低的应力
- 专利标题: Integrated circuit packages with reduced stress on die and associated substrates, assemblies, and systems
- 专利标题(中): 集成电路封装,在裸片和相关的基板,组件和系统上具有降低的应力
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申请号: US10403313申请日: 2003-03-31
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公开(公告)号: US06989586B2公开(公告)日: 2006-01-24
- 发明人: Sairam Agraharam , Carlton Hanna , Vasudeva Atluri , Dongming He
- 申请人: Sairam Agraharam , Carlton Hanna , Vasudeva Atluri , Dongming He
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Schwegman, Lunberg, Woessner & Kluth, P.A.
- 主分类号: H01L23/02
- IPC分类号: H01L23/02
摘要:
Mechanical stresses are reduced between an electronic component having relatively low fracture toughness and a substrate having relatively greater fracture toughness. In an embodiment, the component may be a die having mounting contacts formed of a low yield strength material, such as solder. A package substrate has columnar lands formed of a relatively higher yield strength material, such as copper, having a relatively higher melting point than the component contacts and having a relatively high current-carrying capacity. The component contacts may be hemispherical in shape. The lands may be substantially cylinders, truncated cones or pyramids, inverted truncated cones or pyramids, or other columnar shapes. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.
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