Invention Grant
US06989607B2 Stress reduction in flip-chip PBGA packaging by utilizing segmented chips and/or chip carriers
失效
通过利用分段芯片和/或芯片载体来降低倒装芯片PBGA封装
- Patent Title: Stress reduction in flip-chip PBGA packaging by utilizing segmented chips and/or chip carriers
- Patent Title (中): 通过利用分段芯片和/或芯片载体来降低倒装芯片PBGA封装
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Application No.: US10629469Application Date: 2003-07-29
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Publication No.: US06989607B2Publication Date: 2006-01-24
- Inventor: Krishna Darbha , Miguel A. Jimarez , Matthew M. Reiss , Sanjeev B. Sathe , Charles G. Woychik
- Applicant: Krishna Darbha , Miguel A. Jimarez , Matthew M. Reiss , Sanjeev B. Sathe , Charles G. Woychik
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Schmeiser, Olsen & Watts
- Agent William H. Steinberg
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40
Abstract:
A method and structure to electrically couple a semiconductor device to a substrate that is divided into a plurality of segments. Alternatively, a semiconductor device may be divided into a plurality of segments and the plurality of segments are electrically coupled to a single substrate.
Public/Granted literature
- US20040021205A1 Stress reduction in flip-chip PBGA packaging by utilizing segmented chips and/or chip carriers Public/Granted day:2004-02-05
Information query
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