公开(公告)号：US06955982B2

公开(公告)日：2005-10-18

申请号：US10715649

申请日：2003-11-18

Applicant: Miguel A. Jimarez ,  Cynthia S. Milkovich ,  Mark V. Pierson

Inventor： Miguel A. Jimarez ,  Cynthia S. Milkovich ,  Mark V. Pierson

IPC: H01R12/04 ,  B23K1/00 ,  H01L21/48 ,  H01L21/60 ,  H01L23/485 ,  H01L23/498 ,  H01R4/02 ,  H05K1/14 ,  H05K3/00 ,  H05K3/28 ,  H05K3/34 ,  H05K3/36 ,  H01L21/44 ,  B23K31/00 ,  B23K31/02 ,  B21D39/00

CPC classification number: H01L24/12 ,  B23K1/0016 ,  B23K2101/42 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05671 ,  H01L2224/10126 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81013 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/351 ,  H05K3/0032 ,  H05K3/3436 ,  H05K2201/0379 ,  H05K2201/10977 ,  H05K2201/10992 ,  H05K2203/0415 ,  H05K2203/043 ,  H05K2203/0465 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2924/00014

Abstract: An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a structure that couples a first conductive body of a first substrate to a second conductive body of a second substrate (e.g., a chip to a chip carrier; a chip carrier to a circuit card). The melting point of the first conductive body exceeds the melting point of the second conductive body. The second conductive body may include eutectic lead-tin alloy, while the first conductive body may include non-eutectic lead-tin alloy. A portion of the first conductive body is coated with, or volumetrically surrounded by, a material that is nonsolderable and nonconductive. The first and second conductive bodies are coupled mechanically and electrically by surface adhesion at an uncoated portion of the first conductive body, by application of a temperature that lies between the melting points of the first and second conductive bodies.

Abstract translation: 一种电结构和相关制造方法，用于减少将第一衬底的第一导体与第二衬底的第二导电体（例如，芯片耦合到芯片载体;芯片载体）的结构中的热诱导应变 到电路卡）。 第一导电体的熔点超过第二导电体的熔点。 第二导电体可以包括共晶铅锡合金，而第一导电体可以包括非共晶铅锡合金。 第一导电体的一部分被不可焊接和不导电的材料涂覆或体积地包围。 通过施加位于第一和第二导电体的熔点之间的温度，第一和第二导电体通过在第一导电体的未涂覆部分处的表面粘附机械和电连接。

公开(公告)号：US06818972B2

公开(公告)日：2004-11-16

申请号：US10262023

申请日：2002-09-30

Applicant: Lisa J. Jimarez ,  Miguel A. Jimarez

Inventor： Lisa J. Jimarez ,  Miguel A. Jimarez

IPC: H01L23495

CPC classification number: H01L23/49822 ,  B32B15/08 ,  H01L23/142 ,  H01L2224/16225 ,  H01L2924/01322 ,  H05K1/0271 ,  H05K3/4602 ,  H05K2201/0949 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2201/10734 ,  Y10T428/125 ,  Y10T428/12528 ,  Y10T428/24917 ,  H01L2924/00

Abstract: A method and structure for reducing chip carrier flexing during thermal cycling. A semiconductor chip is coupled to a stiff chip carrier (i.e., a chip carrier having an elastic modulus of at least about 3×105 psi), and there is no stiffener ring on a periphery of the chip carrier. Without the stiffener ring, the chip carrier is able to undergo natural flexing (in contrast with constrained flexing) in response to a temperature change that induces thermal strains due to a mismatch in coefficient of thermal expansion between the chip and the chip carrier. If the temperature at the chip carrier changes from room temperature to a temperature of about −40° C., a maximum thermally induced displacement of a surface of the chip carrier is at least about 25% less if the stiffener ring is absent than if the stiffener ring is present. Since a propensity for cracking of the stiff chip carrier increases as the thermally induced displacement increases, the present invention, which avoids use of the stiffener ring, improves a structural integrity of the chip carrier.

Abstract translation: 用于减少热循环期间芯片载体弯曲的方法和结构。 半导体芯片耦合到刚性芯片载体（即具有至少约3×10 5 psi的弹性模量的芯片载体），并且在芯片载体的外围没有加强环。 没有加强环，芯片载体响应于由于芯片和芯片载体之间的热膨胀系数不匹配而引起热应变的温度变化，能够经受自然弯曲（与受限制的弯曲相反）。 如果芯片载体上的温度从室温变化到约-40℃的温度，如果加强环不存在，则芯片载体的表面的最大热诱导位移比如下 存在加强环。 由于热引起的位移增加，刚性芯片载体的开裂倾向增加，所以避免使用加强环的本发明改善了芯片载体的结构完整性。

公开(公告)号：US06750405B1

公开(公告)日：2004-06-15

申请号：US09690485

申请日：2000-10-17

Applicant: Kenneth Fallon ,  Miguel A. Jimarez ,  Ross W. Keesler ,  John M. Lauffer ,  Roy H. Magnuson ,  Voya R. Markovich ,  Irv Memis ,  Jim P. Paoletti ,  Marybeth Perrino ,  John A. Welsh ,  William E. Wilson

Inventor： Kenneth Fallon ,  Miguel A. Jimarez ,  Ross W. Keesler ,  John M. Lauffer ,  Roy H. Magnuson ,  Voya R. Markovich ,  Irv Memis ,  Jim P. Paoletti ,  Marybeth Perrino ,  John A. Welsh ,  William E. Wilson

IPC: H01R1204

CPC classification number: H05K3/445 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/056 ,  H05K1/113 ,  H05K3/0023 ,  H05K3/0052 ,  H05K3/0094 ,  H05K3/06 ,  H05K3/108 ,  H05K3/426 ,  H05K3/429 ,  H05K3/44 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0919 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/096 ,  H05K2201/10734 ,  H05K2203/0323 ,  H05K2203/0574 ,  H05K2203/0733 ,  H05K2203/1394 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method of forming a printed circuit board or circuit card is provided with a metal layer which serves as a power plane sandwiched between a pair of photoimageable dielectric layers. Photoformed metal filled vias and photoformed plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials and connected to the vias and plated through holes. A border may be around the board or card including a metal layer terminating in from the edge of one of the dielectric layers. A copper foil is provided with clearance holes. First and second layers of photoimageable curable dielectric material is disposed on opposite sides of the copper which are photoimageable material. The patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. At the clearance holes in the copper, through holes are developed where holes were patterned in both dielectric layers. Thereafter, the surfaces of the photoimageable material, vias and through holes are metalized by copper plating. This is preferably done by protecting the remainder of the circuitry with photoresist and utilizing photolithographic techniques. The photoresist is thereafter removed, leaving a circuit board or card having metalization on both sides, vias extending from both sides to the copper layer in the center, plated through holes connecting the two outer circuitized copper layers.

Abstract translation: 形成印刷电路板或电路卡的方法设置有用作夹在一对可光成像的电介质层之间的电力平面的金属层。 光刻图形金属填充的通孔和光成像的电镀通孔位于光图案化材料中，信号电路位于每个介电材料的表面上，并连接到通孔和电镀通孔。 边界可以在板或卡周围，包括从电介质层之一的边缘终止的金属层。 铜箔上设有间隙孔。 可光成像的可固化介电材料的第一和第二层设置在作为可光成像的材料的铜的相对侧上。 图案在可光成象材料的第一层和第二层上显影，以通过通孔显露金属层。 在铜中的间隙孔处，通孔被开发成在两个电介质层中图案化孔。 此后，可光成像材料，通孔和通孔的表面通过镀铜进行金属化。 这优选通过用光致抗蚀剂和利用光刻技术保护电路的其余部分来实现。 然后去除光致抗蚀剂，留下在两侧具有金属化的电路板或卡，其中心的两侧延伸到铜层，通孔连接两个外部电路化的铜层。

公开(公告)号：US07328506B2

公开(公告)日：2008-02-12

申请号：US10281463

申请日：2002-10-25

Applicant: Miguel A. Jimarez ,  Ross W. Keesler ,  Voya R. Markovich ,  Rajinder S. Rai ,  Cheryl L. Tytran-Palomaki

Inventor： Miguel A. Jimarez ,  Ross W. Keesler ,  Voya R. Markovich ,  Rajinder S. Rai ,  Cheryl L. Tytran-Palomaki

IPC: H01K3/10

CPC classification number: H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H05K1/112 ,  H05K3/28 ,  H05K3/3457 ,  H05K3/3484 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/09863 ,  H05K2203/043 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method for forming a plated microvia interconnect. An external dielectric layer (EDL) is mounted on a surface of the substrate and is in direct mechanical contact with a conductive element included in the surface. An opening formed in the EDL exposes the conductive element and creates a microvia in the EDL. A sidewall and bottom wall surface of the microvia is treated to promote copper adhesion to the sidewall and bottom wall surfaces. The sidewall and bottom wall surfaces are plated to form a layer of copper thereon. The layer of copper is in direct mechanical and electrical contact with the conductive element. A wet solder paste deposited on the layer of copper overfills a remaining portion of the microvia. The solder paste is reflowed to form a solder bump in and over the remaining portion of the microvia to form the plated microvia interconnect.

Abstract translation: 一种形成电镀微孔互连的方法。 外部电介质层（EDL）安装在基板的表面上，并且与包括在表面中的导电元件直接机械接触。 EDL中形成的开口露出导电元件，并在EDL中产生微孔。 处理微孔的侧壁和底壁表面以促进铜附着到侧壁和底壁表面。 侧壁和底壁表面被电镀以在其上形成一层铜层。 铜层与导电元件直接机械和电接触。 沉积在铜层上的湿焊膏过量填充微孔的剩余部分。 焊膏被回流以在微孔的剩余部分中和上方形成焊料凸块以形成电镀微孔互连。

公开(公告)号：US06528179B1

公开(公告)日：2003-03-04

申请号：US09691935

申请日：2000-10-19

Applicant: Lisa J. Jimarez ,  Miguel A. Jimarez

Inventor： Lisa J. Jimarez ,  Miguel A. Jimarez

IPC: H01L2912

CPC classification number: H01L23/49822 ,  B32B15/08 ,  H01L23/142 ,  H01L2224/16225 ,  H01L2924/01322 ,  H05K1/0271 ,  H05K3/4602 ,  H05K2201/0949 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2201/10734 ,  Y10T428/125 ,  Y10T428/12528 ,  Y10T428/24917 ,  H01L2924/00

Abstract: A method and structure for reducing chip carrier flexing during thermal cycling. A semiconductor chip is coupled to a stiff chip carrier (i.e., a chip carrier having an elastic modulus of at least about 3×105 psi), and there is no stiffener ring on a periphery of the chip carrier. Without the stiffener ring, the chip carrier is able to undergo natural flexing (in contrast with constrained flexing) in response to a temperature change that induces thermal strains due to a mismatch in coefficient of thermal expansion between the chip and the chip carrier. If the temperature at the chip carrier changes from room temperature to a temperature of about −40° C., a maximum thermally induced displacement of a surface of the chip carrier is at least about 25% less if the stiffener ring is absent than if the stiffener ring is present. Since a propensity for cracking of the stiff chip carrier increases as the thermally induced displacement increases, the present invention, which avoids use of the stiffener ring, improves a structural integrity of the chip carrier.

Abstract translation: 用于减少热循环期间芯片载体弯曲的方法和结构。 半导体芯片耦合到刚性芯片载体（即具有至少约3×10 5 psi的弹性模量的芯片载体），并且在芯片载体的外围没有加强环。 没有加强环，芯片载体响应于由于芯片和芯片载体之间的热膨胀系数不匹配而引起热应变的温度变化，能够经受自然弯曲（与受限制的弯曲相反）。 如果芯片载体上的温度从室温变化到约-40℃的温度，如果加强环不存在，则芯片载体的表面的最大热诱导位移比如下 存在加强环。 由于热引起的位移增加，刚性芯片载体的开裂倾向增加，所以避免使用加强环的本发明改善了芯片载体的结构完整性。

公开(公告)号：US06497943B1

公开(公告)日：2002-12-24

申请号：US09503395

申请日：2000-02-14

Applicant: Lisa J. Jimarez ,  Miguel A. Jimarez ,  Mark V. Pierson

Inventor： Lisa J. Jimarez ,  Miguel A. Jimarez ,  Mark V. Pierson

IPC: B32B300

CPC classification number: B32B15/08 ,  B32B15/20 ,  B32B17/10229 ,  B32B2250/40 ,  B32B2425/00 ,  H01L23/142 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01322 ,  H05K1/0271 ,  H05K3/4602 ,  H05K2201/0949 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2201/10734 ,  Y10T428/24917 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A surface metal balancing structure for a chip carrier, and an associated method of fabrication, to reduce or eliminate thermally induced chip carrier flexing. A substrate, such as a chip carrier made of organic dielectric material, is formed and includes: internal circuitization layers, a plated through hole, and outer layers comprised of an allylated polyphenylene ether. A stiffener ring for mechanically stabilizing the substrate is bonded to an outer portion, such as an outer perimeter portion, of the top surface of the substrate, in light of the soft and conformal organic material of the substrate. The top and bottom surfaces of the substrate have metal structures, such as copper pads and copper circuitization, wherein a surface area (A) multiplied by a coefficient of thermal expansion (C) is greater for the metal structure at the bottom surface than for the metal structure at the top surface. A metal pattern is adjacent to the top surface so as to make the product AC of metal structures at or near the top and bottom surfaces approximately equal. The metal pattern reduces or eliminates flexing of the substrate in an elevated temperature environment, such as during a reflow of solder that couples a semiconductor chip to the substrate.

Abstract translation: 用于芯片载体的表面金属平衡结构以及相关的制造方法，以减少或消除热诱导的芯片载体弯曲。 形成诸如由有机电介质材料制成的芯片载体的衬底，其包括：内部电路层，电镀通孔和由烯丙基化聚苯醚构成的外层。 根据衬底的软和保形有机材料，用于机械稳定衬底的加强环被结合到衬底的顶表面的外部部分，例如外周部分。 衬底的顶表面和底表面具有诸如铜焊盘和铜电路的金属结构，其中在底表面处的金属结构的表面积（A）乘以热膨胀系数（C）大于对于 金属结构在顶面。 金属图案与顶表面相邻，以使金属结构的产品AC在顶表面和底表面处或附近大致相等。 金属图案减少或消除了在升高的温度环境中的衬底的弯曲，例如在将半导体芯片耦合到衬底的焊料的回流期间。

公开(公告)号：US5542601A

公开(公告)日：1996-08-06

申请号：US394684

申请日：1995-02-24

Applicant: Kenneth M. Fallon ,  Miguel A. Jimarez ,  Joseph E. Zdimal

Inventor： Kenneth M. Fallon ,  Miguel A. Jimarez ,  Joseph E. Zdimal

IPC: H01L21/60 ,  H01L23/13 ,  H05K3/34

CPC classification number: H01L24/81 ,  H01L23/13 ,  H01L2224/16 ,  H01L2224/75 ,  H01L2224/75252 ,  H01L2224/75743 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/15787

Abstract: A new rework process for semiconductor chips mounted in a flip chip configuration, via solder balls, on an organic substrate is disclosed.

Abstract translation: 公开了一种通过焊球在有机衬底上以倒装芯片配置安装的半导体芯片的新的返工工艺。

公开(公告)号：US07353590B2

公开(公告)日：2008-04-08

申请号：US11224191

申请日：2005-09-12

Applicant: Kenneth Fallon ,  Miguel A. Jimarez ,  Ross W. Keesler ,  John M. Lauffer ,  Roy H. Magnuson ,  Voya R. Markovich ,  Irv Memis ,  Jim P. Paoletti ,  Marybeth Perrino ,  John A. Welsh ,  William E. Wilson

Inventor： Kenneth Fallon ,  Miguel A. Jimarez ,  Ross W. Keesler ,  John M. Lauffer ,  Roy H. Magnuson ,  Voya R. Markovich ,  Irv Memis ,  Jim P. Paoletti ,  Marybeth Perrino ,  John A. Welsh ,  William E. Wilson

IPC: H05K3/36

CPC classification number: H05K3/445 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/056 ,  H05K1/113 ,  H05K3/0023 ,  H05K3/0052 ,  H05K3/0094 ,  H05K3/06 ,  H05K3/108 ,  H05K3/426 ,  H05K3/429 ,  H05K3/44 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0919 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/096 ,  H05K2201/10734 ,  H05K2203/0323 ,  H05K2203/0574 ,  H05K2203/0733 ,  H05K2203/1394 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method of forming a printed circuit card with a metal power plane layer between two photoimageable dielectric layers is provided. Photoformed metal filled vias and plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials connected to the vias and plated through holes. A border may be around the card including a metal layer terminating in from the edge of one of the dielectric layers. Copper foil with clearance holes is provided. First and second layers of photoimageable curable dielectric material are on opposite sides of the copper. Patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. Through holes are developed where holes were patterned in both dielectric layers. The surfaces of the photoimageable material, vias and through holes are metallized by copper plating, preferably using photoresist.

Abstract translation: 提供了一种在两个可光成像的电介质层之间形成具有金属功率平面层的印刷电路卡的方法。 光刻图形的金属填充通孔和电镀通孔位于光图案化材料中，信号电路位于连接到通孔和电镀通孔的每个介电材料的表面上。 边框可以在卡的周围，包括从电介质层之一的边缘终止的金属层。 提供带有间隙孔的铜箔。 第一层和第二层可光成像的可固化电介质材料位于铜的相对两侧。 在可光成像材料的第一层和第二层上形成图案以通过通孔显露金属层。 开发了通孔，在两个电介质层中对其进行图案化。 可光成像材料，通孔和通孔的表面通过镀铜进行金属化，优选使用光致抗蚀剂。

公开(公告)号：US06989607B2

公开(公告)日：2006-01-24

申请号：US10629469

申请日：2003-07-29

Applicant: Krishna Darbha ,  Miguel A. Jimarez ,  Matthew M. Reiss ,  Sanjeev B. Sathe ,  Charles G. Woychik

Inventor： Krishna Darbha ,  Miguel A. Jimarez ,  Matthew M. Reiss ,  Sanjeev B. Sathe ,  Charles G. Woychik

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/49833 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15151 ,  H01L2924/00012

Abstract: A method and structure to electrically couple a semiconductor device to a substrate that is divided into a plurality of segments. Alternatively, a semiconductor device may be divided into a plurality of segments and the plurality of segments are electrically coupled to a single substrate.

Abstract translation: 将半导体器件电耦合到被分成多个段的衬底的方法和结构。 或者，半导体器件可以被划分成多个段，并且多个段电耦合到单个衬底。

公开(公告)号：US06583517B1

公开(公告)日：2003-06-24

申请号：US10119491

申请日：2002-04-09

Applicant: Miguel A. Jimarez

Inventor： Miguel A. Jimarez

IPC: H01L2348

CPC classification number: H01L24/16 ,  H01L23/488 ,  H01L24/05 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/16 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/351 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/0367 ,  H05K2201/09736 ,  H05K2201/09745 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/01011 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method and structure to electrically and mechanically join a first a first electrically conductive pad on a first substrate to a second electrically conductive pad on a second substrate using a solder joint that includes a low-melt solder alloy composition. The second electrically conductive pad has a geometry that compels a gap size of a gap between the first substrate and the second substrate to exceed a distance between the first substrate and a surface of the second pad.

Abstract translation: 一种使用包括低熔点焊料合金组合物的焊点将第一基板上的第一第一导电焊盘电连接到第二基板上的第二导电焊盘的方法和结构。 第二导电焊盘具有几何形状，其强迫第一基板和第二基板之间的间隙的间隙尺寸超过第一基板和第二垫的表面之间的距离。