发明授权
- 专利标题： Implanted barrier layer to improve line reliability and method of forming same
- 专利标题（中）： 植入障碍层提高线路可靠性及其形成方法
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申请号： US10209060申请日： 2002-07-31
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公开(公告)号： US06992004B1公开(公告)日： 2006-01-31
- 发明人: Paul R. Besser , Matthew S. Buynoski , Minh Q. Tran , Pin-Chin Connie Wang , Lu You , Sergey D. Lopatin , Jeremias D. Romero
- 申请人： Paul R. Besser , Matthew S. Buynoski , Minh Q. Tran , Pin-Chin Connie Wang , Lu You , Sergey D. Lopatin , Jeremias D. Romero
- 申请人地址： US CA Sunnyvale
- 专利权人： Advanced Micro Devices, Inc.
- 当前专利权人： Advanced Micro Devices, Inc.
- 当前专利权人地址： US CA Sunnyvale
- 代理机构： Foley & Lardner LLP
- 主分类号： H01L21/44
- IPC分类号： H01L21/44
摘要：
A method for manufacturing an integrated circuit having improved electromigration characteristics includes forming an aperture in an interlevel dielectric layer and providing a barrier layer in the aperture. The aperture is filled with a metal material and a barrier layer is provided above the metal material. An intermetallic region can be formed at an interface of the metal material and the barrier layer. The intermetallic material can be formed by implantation of species.