发明授权
- 专利标题: Optimization apparatus that decreases delays in pipeline processing of loop and computer-readable storage medium storing optimization program
- 专利标题(中): 降低循环流水线处理延迟和存储优化程序的计算机可读存储介质的优化装置
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申请号: US09798490申请日: 2001-03-02
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公开(公告)号: US06993756B2公开(公告)日: 2006-01-31
- 发明人: Hajime Ogawa , Shuichi Takayama
- 申请人: Hajime Ogawa , Shuichi Takayama
- 申请人地址: JP Osaka
- 专利权人: Matsushita Electric Industrial Co., Ltd.
- 当前专利权人: Matsushita Electric Industrial Co., Ltd.
- 当前专利权人地址: JP Osaka
- 优先权: JP2000-059506 20000303
- 主分类号: G06F9/45
- IPC分类号: G06F9/45
摘要:
An optimization apparatus is capable of improving the execution efficiency of a loop that includes a loop carry dependency between consecutive iterations of the loop. For example, a value resulting from one iteration is used in an immediately following iteration. When the arithmetic expression “a[i+1]=a[i]*3+2;” is included in a loop body, and a value resulting from the arithmetic expression “a[i+1]=a[i]*3+2;” in one iteration is used in a following iteration, execution delays occur in pipeline processing of the loop. Here, the arithmetic expression “a[i+1]=a[i]*3+2;” is transformed into the arithmetic expression “a[i+4]=a[i]*81+80;” to expand the dependency distance. By doing so, the execution delays can be decreased.