公开(公告)号：US09409272B2

公开(公告)日：2016-08-09

申请号：US13442012

申请日：2012-04-09

申请人： Junichi Tezuka ,  Hajime Ogawa

发明人： Junichi Tezuka ,  Hajime Ogawa

IPC分类号： B23Q17/24 ,  G05B19/4068 ,  H04N13/02 ,  H04N13/04

CPC分类号： B23Q17/2409 ,  G05B19/4068 ,  G05B2219/35318 ,  G05B2219/35322 ,  G05B2219/35349 ,  H04N13/204 ,  H04N13/30

摘要： A tool path display apparatus, configured to display a three-dimensional path of a movable part of a machine tool, calculates three-dimensional coordinate values of the movable part as viewed from a coordinate system secured to a workpiece, thereby determining the three-dimensional path of the movable part. Left- and right-eye stereoscopic image data are determined based on the determined three-dimensional path of the movable part, and the determined left- and right-eye stereoscopic image data are displayed on the display apparatus so that they can be viewed by an operator's left and right eyes, respectively.

摘要翻译： 一种刀具路径显示装置，被配置为显示机床的可移动部分的三维路径，计算出从固定在工件上的坐标系观察的可动部分的三维坐标值，从而确定三维 可移动部分的路径。 基于确定的可移动部分的三维路径确定左眼立体图像数据和右眼立体图像数据，并且确定的左眼立体图像数据和右眼立体图像数据被显示在显示装置上，使得它们可以被 操作者的左眼和右眼分别。

公开(公告)号：US08418157B2

公开(公告)日：2013-04-09

申请号：US12706329

申请日：2010-02-16

申请人： Hajime Ogawa ,  Taketo Heishi ,  Toshiyuki Sakata ,  Shuichi Takayama ,  Shohei Michimoto ,  Tomoo Hamada ,  Ryoko Miyachi

发明人： Hajime Ogawa ,  Taketo Heishi ,  Toshiyuki Sakata ,  Shuichi Takayama ,  Shohei Michimoto ,  Tomoo Hamada ,  Ryoko Miyachi

IPC分类号： G06F9/45

CPC分类号： G06F8/443

摘要： A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a “if” conversion unit, and a pair instruction generation unit) that performs individual optimization processing designated by options and pragmas from a user, following the directives and the like from the analysis unit, etc. The global region allocation unit performs optimization processing, following designation of the maximum data size of variables to be allocated to a global region, designation of variables to be allocated to the global region, and options and pragmas regarding designation of variables not to be allocated in the global region.

摘要翻译： 编译器包括检测用户到编译器的指令（选项和编译指示）的分析单元，由处理单元（全局区域分配单元，软件流水线单元，循环展开单元， 如果转换单元和配对指令生成单元）执行来自用户的选项和编译指示的单独优化处理，遵循来自分析单元的指令等。全局区域分配单元执行优化处理，在指定 要分配给全局区域的变量的最大数据大小，要分配给全局区域的变量的指定，以及关于在全局区域中未分配的变量的指定的选项和编译指示。

公开(公告)号：US20120257276A1

公开(公告)日：2012-10-11

申请号：US13442012

申请日：2012-04-09

申请人： Junichi TEZUKA ,  Hajime OGAWA

发明人： Junichi TEZUKA ,  Hajime OGAWA

IPC分类号： G02B27/22

CPC分类号： B23Q17/2409 ,  G05B19/4068 ,  G05B2219/35318 ,  G05B2219/35322 ,  G05B2219/35349 ,  H04N13/204 ,  H04N13/30

摘要： A tool path display apparatus, configured to display a three-dimensional path of a movable part of a machine tool, calculates three-dimensional coordinate values of the movable part as viewed from a coordinate system secured to a workpiece, thereby determining the three-dimensional path of the movable part. Left- and right-eye stereoscopic image data are determined based on the determined three-dimensional path of the movable part, and the determined left- and right-eye stereoscopic image data are displayed on the display apparatus so that they can be viewed by an operator's left and right eyes, respectively.

摘要翻译： 一种刀具路径显示装置，被配置为显示机床的可移动部分的三维路径，计算出从固定在工件上的坐标系观察的可动部分的三维坐标值，从而确定三维 可移动部分的路径。 基于确定的可移动部分的三维路径确定左眼立体图像数据和右眼立体图像数据，并且确定的左眼立体图像数据和右眼立体图像数据被显示在显示装置上，使得它们可以被 操作者的左眼和右眼分别。

公开(公告)号：US08151254B2

公开(公告)日：2012-04-03

申请号：US11790215

申请日：2007-04-24

申请人： Taketo Heishi ,  Toshiyuki Sakata ,  Hajime Ogawa ,  Ryoko Miyachi ,  Shuji Miyasaka ,  Tomokazu Ishikawa

发明人： Taketo Heishi ,  Toshiyuki Sakata ,  Hajime Ogawa ,  Ryoko Miyachi ,  Shuji Miyasaka ,  Tomokazu Ishikawa

IPC分类号： G06F9/45

CPC分类号： G06F8/443 ,  G06F8/425 ,  G06F8/427 ,  G06F8/4441

摘要： An operator definition file 102 and the like included in a source program 101 and a compiler 100 that translates the source program 101 into a machine language program 105 are provided. The operator definition file 102 includes definitions of various fixed point type operators by class definitions. The compiler 100 can generate effectively advanced and specific instructions that a processor executes and make improvements through expanding functions and the like without repeating frequently upgrading of the version of the compiler itself. The compiler 100 is made up of an intermediate code generation unit 121 that generates intermediate codes, a machine language instruction substitution unit 122 that substitutes the intermediate codes referring to classes defined by the operator definition file 102 with machine language instructions and an optimization unit 130 that performs optimization targeting the intermediate codes including the substituted machine language instructions.

摘要翻译： 提供包括在源程序101中的操作者定义文件102等以及将源程序101转换为机器语言程序105的编译器100。 操作者定义文件102包括通过类定义的各种定点类型操作符的定义。 编译器100可以生成有效的高级特定指令，处理器执行并通过扩展功能等进行改进，而不会重复频繁升级编译器本身的版本。 编译器100由生成中间代码的中间代码生成单元121构成，机器语言指令替换单元122，其使用机器语言指令代替参考由操作者定义文件102定义的类别的中间代码和优化单元130， 执行针对包括替代机器语言指令的中间代码的优化。

公开(公告)号：US20100175056A1

公开(公告)日：2010-07-08

申请号：US12706329

申请日：2010-02-16

申请人： Hajime OGAWA ,  Taketo Heishi ,  Toshiyuki Sakata ,  Shuichi Takayama ,  Shohei Michimoto ,  Tomoo Hamada ,  Ryoko Miyachi

发明人： Hajime OGAWA ,  Taketo Heishi ,  Toshiyuki Sakata ,  Shuichi Takayama ,  Shohei Michimoto ,  Tomoo Hamada ,  Ryoko Miyachi

IPC分类号： G06F9/45 ,  G06F9/44

CPC分类号： G06F8/443

摘要： A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a “if” conversion unit, and a pair instruction generation unit) that performs individual optimization processing designated by options and pragmas from a user, following the directives and the like from the analysis unit, etc. The global region allocation unit performs optimization processing, following designation of the maximum data size of variables to be allocated to a global region, designation of variables to be allocated to the global region, and options and pragmas regarding designation of variables not to be allocated in the global region.

摘要翻译： 编译器包括检测用户到编译器的指令（选项和编译指示）的分析单元，由处理单元（全局区域分配单元，软件流水线单元，循环展开单元， 根据来自分析单元等的指令等，执行由用户选择和编译指定的单独优化处理的“if”转换单元和一对指令生成单元）。全局区域分配单元执行优化处理 指定要分配给全球区域的变量的最大数据大小，指定要分配给全局区域的变量，以及关于指定未分配给全局区域的变量的选项和编译指示。

公开(公告)号：US07689976B2

公开(公告)日：2010-03-30

申请号：US10950397

申请日：2004-09-28

申请人： Yasuhiro Yamamoto ,  Hajime Ogawa ,  Taketo Heishi ,  Shohei Michimoto

发明人： Yasuhiro Yamamoto ,  Hajime Ogawa ,  Taketo Heishi ,  Shohei Michimoto

IPC分类号： G06F9/45 ,  G06F9/44

CPC分类号： G06F8/4442

摘要： A compiler capable of increasing the hit rate of the cache memory is provided that targets a computer having a cache memory, and that converts a source program into an object program. The compiler causes a computer to analyze group information that is used for grouping data objects included in the source program, and places the data objects into groups based on a result of the analysis. The compiler also causes the computer to generate an object program based on a result of the grouping, where the object program does not allow data objects belonging to different groups to be laid out in any blocks with the same set number on the cache memory.

摘要翻译： 提供了能够提高高速缓冲存储器的命中率的编译器，其目标是具有高速缓冲存储器的计算机，并且将源程序转换为对象程序。 编译器使计算机分析用于对源程序中包含的数据对象进行分组的组信息，并根据分析结果将数据对象放入组中。 编译器还使得计算机基于分组的结果生成对象程序，其中对象程序不允许属于不同组的数据对象被布置在高速缓冲存储器上具有相同设定编号的任何块中。

公开(公告)号：US20080295082A1

公开(公告)日：2008-11-27

申请号：US12107450

申请日：2008-04-22

申请人： Teruo KAWABATA ,  Masatsugu DAIMON ,  Taketo HEISHI ,  Hajime OGAWA

发明人： Teruo KAWABATA ,  Masatsugu DAIMON ,  Taketo HEISHI ,  Hajime OGAWA

IPC分类号： G06F9/45

CPC分类号： G06F8/4441

摘要： A program re-writing method which re-writes an inputted program into a program for a processor for controlling whether or not a process is executed based on a yes or no execution flag, said program re-writing method including: inserting a comparison process into the inputted program, the comparison process comparing first address information, which is memory address information accessed by a first memory access process included in the inputted program, and second address information, which is address information of a memory accessed by a second memory access process included in the inputted program, and writing a comparison result into the yes or no execution flag; and inserting a yes or no execution flag-attached logic preservation process into the inputted program, the yes or no execution flag-attached logic preservation process being a process executed based on a value of the yes or no execution flag and preserving the same result as a result of the inputted program when executed.

摘要翻译： 一种程序重写方法，其将输入的程序重写到用于处理器的程序中，用于基于是或否执行标志来控制是否执行处理，所述程序重写方法包括：将比较处理插入到 所输入的程序，比较第一地址信息的比较处理，第一地址信息是由包括在输入的程序中的第一存储器访问处理访问的存储器地址信息和作为​​包括第二存储器访问处理访问的存储器的地址信息的第二地址信息 在输入的程序中，将比较结果写入是或否执行标志; 并且在输入的程序中插入“是”或“否”执行标志附加的逻辑保存处理，“是”或“否”执行标志附加的逻辑保存处理是基于“是”或“否”执行标志的值执行的处理，并且保持与 执行时输入程序的结果。

公开(公告)号：US07386844B2

公开(公告)日：2008-06-10

申请号：US10760429

申请日：2004-01-21

申请人： Taketo Heishi ,  Hajime Ogawa ,  Takenobu Tani ,  Yukihiro Sasagawa

发明人： Taketo Heishi ,  Hajime Ogawa ,  Takenobu Tani ,  Yukihiro Sasagawa

IPC分类号： G06F9/45 ,  G06F1/00 ,  G06F1/26

CPC分类号： G06F9/3001 ,  G06F8/4432 ,  G06F9/30156 ,  G06F9/3836 ,  G06F9/3838 ,  Y02D10/41

摘要： A compiler apparatus is capable of generating instruction sequences causing a processor to operate with lower power consumption. The compiler apparatus translates a source program into a machine language program for a processor including execution units which can execute instructions in parallel, and including instruction issue units which issue the instructions executed, respectively, by the execution units. The compiler apparatus includes a parser unit operable to parse the source program, an intermediate code conversion unit operable to convert the parsed source program into intermediate codes, an optimization unit operable to optimize the intermediate codes to reduce a hamming distance between instructions from the same instruction issue unit in consecutive instruction cycles, and includes a code generation unit operable to convert the optimized intermediate codes into machine language instructions.

摘要翻译： 编译装置能够产生指令序列，使得处理器以更低的功耗进行操作。 编译装置将源程序转换为用于处理器的机器语言程序，所述处理器包括可并行执行指令的执行单元，并且包括执行单元分别执行执行指令的指令发布单元。 编译器装置包括可解析源程序的解析器单元，可操作以将解析的源程序转换为中间代码的中间代码转换单元，可优化中间代码以减少来自相同指令的指令之间的汉明距离的优化单元 发布单元，并且包括可以将优化的中间代码转换成机器语言指令的代码生成单元。

公开(公告)号：US20080046690A1

公开(公告)日：2008-02-21

申请号：US11896370

申请日：2007-08-31

申请人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

发明人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

IPC分类号： G06F9/302

CPC分类号： G06F9/30025 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167

摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

公开(公告)号：US20070256065A1

公开(公告)日：2007-11-01

申请号：US11790215

申请日：2007-04-24

申请人： Taketo Heishi ,  Toshiyuki Sakata ,  Hajime Ogawa ,  Ryoko Miyachi ,  Shuji Miyasaka ,  Tomokazu Ishikawa

发明人： Taketo Heishi ,  Toshiyuki Sakata ,  Hajime Ogawa ,  Ryoko Miyachi ,  Shuji Miyasaka ,  Tomokazu Ishikawa

IPC分类号： G06F9/45

CPC分类号： G06F8/443 ,  G06F8/425 ,  G06F8/427 ,  G06F8/4441

摘要： An operator definition file 102 and the like included in a source program 101 and a compiler 100 that translates the source program 101 into a machine language program 105 are provided. The operator definition file 102 includes definitions of various fixed point type operators by class definitions. The compiler 100 can generate effectively advanced and specific instructions that a processor executes and make improvements through expanding functions and the like without repeating frequently upgrading of the version of the compiler itself. The compiler 100 is made up of an intermediate code generation unit 121 that generates intermediate codes, a machine language instruction substitution unit 122 that substitutes the intermediate codes referring to classes defined by the operator definition file 102 with machine language instructions and an optimization unit 130 that performs optimization targeting the intermediate codes including the substituted machine language instructions.