发明授权
US06996702B2 Processing unit with cross-coupled ALUs/accumulators and input data feedback structure including constant generator and bypass to reduce memory contention
失效
处理单元具有交叉耦合的ALU /累加器和输入数据反馈结构，包括恒定发生器和旁路以减少内存争用
- 专利标题： Processing unit with cross-coupled ALUs/accumulators and input data feedback structure including constant generator and bypass to reduce memory contention
- 专利标题（中）： 处理单元具有交叉耦合的ALU /累加器和输入数据反馈结构，包括恒定发生器和旁路以减少内存争用
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申请号： US10209109申请日： 2002-07-30
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公开(公告)号： US06996702B2公开(公告)日： 2006-02-07
- 发明人: Shuhua Xiang , Li Sha , Ping Zhu , Hongjun Yuan , Wei Ni
- 申请人： Shuhua Xiang , Li Sha , Ping Zhu , Hongjun Yuan , Wei Ni
- 申请人地址： US CA Santa Clara
- 专利权人： WIS Technologies, Inc.
- 当前专利权人： WIS Technologies, Inc.
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Fenwick & West
- 主分类号： G06F9/34
- IPC分类号： G06F9/34
摘要：
A processing system includes an arithmetic logic unit (ALU) sub-system that allows data associated with a prior instruction to be preserved for use with a next instruction or subsequent instruction without having to reload the value using an intermediate register. The ALU sub-system includes a pair of ALUs communicatively cross-coupled with a pair of accumulators. The processing system also includes a data selector coupled to the ALU sub-system for use with memory contention prediction. The data selector includes a constant generator that controls storage of data associated with a previous instruction in a bypass element, and a selector to choose between data from a databus element and data stored in the bypass element.