发明授权
US06998682B2 Method of forming a partially depleted silicon on insulator (PDSOI) transistor with a pad lock body extension
有权
用垫锁体延伸形成部分耗尽的绝缘体硅(PDSOI)晶体管的方法
- 专利标题: Method of forming a partially depleted silicon on insulator (PDSOI) transistor with a pad lock body extension
- 专利标题(中): 用垫锁体延伸形成部分耗尽的绝缘体硅(PDSOI)晶体管的方法
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申请号: US11128010申请日: 2005-05-12
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公开(公告)号: US06998682B2公开(公告)日: 2006-02-14
- 发明人: Yeen Tat Chan , Kheng Chok Tee , Yiang Aun Nga , Zhao Lun , Wang Ling Goh , Diing Shenp Ang
- 申请人: Yeen Tat Chan , Kheng Chok Tee , Yiang Aun Nga , Zhao Lun , Wang Ling Goh , Diing Shenp Ang
- 申请人地址: SG Singapore
- 专利权人: Chartered Semiconductor Manufacturing Ltd.
- 当前专利权人: Chartered Semiconductor Manufacturing Ltd.
- 当前专利权人地址: SG Singapore
- 代理商 George O. Saile; Rosemary L.S. Pike
- 主分类号: H01L27/01
- IPC分类号: H01L27/01
摘要:
A MOSFET device structure formed on a silicon on insulator layer, and a process sequence employed to fabricate said MOSFET device structure, has been developed. The process features insulator filled, shallow trench isolation (STI) regions formed in specific locations of the MOSFET device structure for purposes of reducing the risk of parasitic transistor formation underlying a gate structure junction. After formation of either a “T” shaped, or an “H” shaped gate structure, body contact regions of a first conductivity type are formed adjacent to both an STI region and to a component of the gate structure. Formation of a source/drain region of a second conductivity type located on the opposite side of the same STI region, and the same gate structure component, is next performed. Unwanted parasitic transistor formation, which can occur underlying the gate structure via the body contact region and the source/drain region, is prevented by the presence of the separating STI region.
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