公开(公告)号：US06905919B2

公开(公告)日：2005-06-14

申请号：US10628913

申请日：2003-07-29

申请人： Yeen Tat Chan ,  Kheng Chok Tee ,  Yiang Aun Nga ,  Zhao Lun ,  Wang Ling Goh ,  Diing Shenp Ang

发明人： Yeen Tat Chan ,  Kheng Chok Tee ,  Yiang Aun Nga ,  Zhao Lun ,  Wang Ling Goh ,  Diing Shenp Ang

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/84

CPC分类号： H01L29/66772 ,  H01L29/78615

摘要： A MOSFET device structure formed on a silicon on insulator layer, and a process sequence employed to fabricate said MOSFET device structure, has been developed. The process features insulator filled, shallow trench isolation (STI) regions formed in specific locations of the MOSFET device structure for purposes of reducing the risk of parasitic transistor formation underlying a gate structure junction. After formation of either a “T” shaped, or an “H” shaped gate structure, body contact regions of a first conductivity type are formed adjacent to both an STI region and to a component of the gate structure. Formation of a source/drain region of a second conductivity type located on the opposite side of the same STI region, and the same gate structure component, is next performed. Unwanted parasitic transistor formation, which can occur underlying the gate structure via the body contact region and the source/drain region, is prevented by the presence of the separating STI region.

摘要翻译： 已经开发了在绝缘体上硅层上形成的MOSFET器件结构以及用于制造所述MOSFET器件结构的工艺顺序。 该工艺具有在MOSFET器件结构的特定位置形成的绝缘体填充的浅沟槽隔离（STI）区域，用于降低栅极结构结下方的寄生晶体管形成的风险。 在形成“T”形或“H”形栅极结构之后，形成与STI区域和栅极结构的部件相邻的第一导电类型的主体接触区域。 接下来进行位于相同STI区域的相反侧的第二导电类型的源极/漏极区域的形成以及相同的栅极结构部件。 通过存在分离的STI区域可以防止通过体接触区域和源极/漏极区域发生在栅极结构下方的不需要的寄生晶体管形成。

公开(公告)号：US06998682B2

公开(公告)日：2006-02-14

申请号：US11128010

申请日：2005-05-12

申请人： Yeen Tat Chan ,  Kheng Chok Tee ,  Yiang Aun Nga ,  Zhao Lun ,  Wang Ling Goh ,  Diing Shenp Ang

发明人： Yeen Tat Chan ,  Kheng Chok Tee ,  Yiang Aun Nga ,  Zhao Lun ,  Wang Ling Goh ,  Diing Shenp Ang

IPC分类号： H01L27/01

CPC分类号： H01L29/66772 ,  H01L29/78615

摘要： A MOSFET device structure formed on a silicon on insulator layer, and a process sequence employed to fabricate said MOSFET device structure, has been developed. The process features insulator filled, shallow trench isolation (STI) regions formed in specific locations of the MOSFET device structure for purposes of reducing the risk of parasitic transistor formation underlying a gate structure junction. After formation of either a “T” shaped, or an “H” shaped gate structure, body contact regions of a first conductivity type are formed adjacent to both an STI region and to a component of the gate structure. Formation of a source/drain region of a second conductivity type located on the opposite side of the same STI region, and the same gate structure component, is next performed. Unwanted parasitic transistor formation, which can occur underlying the gate structure via the body contact region and the source/drain region, is prevented by the presence of the separating STI region.

摘要翻译： 已经开发了在绝缘体上硅层上形成的MOSFET器件结构以及用于制造所述MOSFET器件结构的工艺顺序。 该工艺具有在MOSFET器件结构的特定位置形成的绝缘体填充的浅沟槽隔离（STI）区域，用于降低栅极结构结下方的寄生晶体管形成的风险。 在形成“T”形或“H”形栅极结构之后，形成与STI区域和栅极结构的部件相邻的第一导电类型的主体接触区域。 接下来进行位于相同STI区域的相反侧的第二导电类型的源极/漏极区域的形成以及相同的栅极结构部件。 通过存在分离的STI区域可以防止通过体接触区域和源极/漏极区域发生在栅极结构下方的不需要的寄生晶体管形成。

公开(公告)号：US07528445B2

公开(公告)日：2009-05-05

申请号：US11380378

申请日：2006-04-26

申请人： Timothy Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

发明人： Timothy Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

IPC分类号： H01L29/76 ,  H01L31/113 ,  H01L21/338

CPC分类号： H01L29/6653 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A system is provided for forming a semiconductor device. Layers of gate dielectric material, gate material, and cap material are formed on a semiconductor substrate. The cap material and a portion of the gate material are processed to form a cap and a gate body portion. A wing on the gate body portion is formed from a remaining portion of the gate material. The gate dielectric material under a portion of the wing on the gate body portion is removed to form a gate dielectric. A lightly-doped source/drain region is formed in the semiconductor substrate using the gate body portion and the wing.

摘要翻译： 提供一种用于形成半导体器件的系统。 在半导体衬底上形成栅介电材料层，栅极材料层和盖材料层。 盖材料和栅极材料的一部分被加工以形成盖和门体部分。 门体部分上的翼部由栅极材料的剩余部分形成。 栅极主体部分的翼部的下方的栅介质材料被去除以形成栅极电介质。 使用门主体部分和机翼，在半导体衬底中形成轻掺杂的源极/漏极区域。

公开(公告)号：US20060180848A1

公开(公告)日：2006-08-17

申请号：US11380378

申请日：2006-04-26

申请人： Timothy Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

发明人： Timothy Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L29/6653 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A system is provided for forming a semiconductor device. Layers of gate dielectric material, gate material, and cap material are formed on a semiconductor substrate. The cap material and a portion of the gate material are processed to form a cap and a gate body portion. A wing on the gate body portion is formed from a remaining portion of the gate material. The gate dielectric material under a portion of the wing on the gate body portion is removed to form a gate dielectric. A lightly-doped source/drain region is formed in the semiconductor substrate using the gate body portion and the wing.

摘要翻译： 提供一种用于形成半导体器件的系统。 在半导体衬底上形成栅介电材料层，栅极材料层和盖材料层。 盖材料和栅极材料的一部分被加工以形成盖和门体部分。 门体部分上的翼部由栅极材料的剩余部分形成。 栅极主体部分的翼部的下方的栅介质材料被去除以形成栅极电介质。 使用门主体部分和机翼，在半导体衬底中形成轻掺杂的源极/漏极区域。

公开(公告)号：US06410429B1

公开(公告)日：2002-06-25

申请号：US09795113

申请日：2001-03-01

申请人： Chaw Sing Ho ,  Kheng Chok Tee ,  Kin Leong Pey ,  G. Karunasiri ,  Soo Jin Chua ,  Kong Hean Lee ,  Alex Kalhung See

发明人： Chaw Sing Ho ,  Kheng Chok Tee ,  Kin Leong Pey ,  G. Karunasiri ,  Soo Jin Chua ,  Kong Hean Lee ,  Alex Kalhung See

IPC分类号： H01L2144

CPC分类号： H01L29/6659 ,  H01L21/2257 ,  H01L21/28518 ,  H01L29/665

摘要： A method for forming a void-free epitaxial cobalt silicide (CoSi2) layer on an ultra-shallow source/drain junction. A patterned silicon structure is cleaned using HF. A first titanium layer, a cobalt layer, and a second titanium layer are successively formed on the patterned silicon substrate. The patterned silicon substrate is annealed at a temperature of between about 550° C. and 580° C. in a nitrogen ambient at atmospheric pressure; whereby the cobalt migrates downward and reacts with the silicon structure to form a CoSi2/CoSi layer, and the first titanium layer migrates upward and the first titanium layer and the second titanium layer react with the nitrigen ambient to form TiN. The TiN and unreacted cobalt are removed. The silicon structure is annealed at a temperature of between about 825° C. and 875° C. to convert the CoSi2/CoSi layer to a CoSi2 layer. The CoSi2 layer can optionally be implanted with impurity ions which are subsequently diffused to form ultra-shallow junctions.

摘要翻译： 在超浅源极/漏极结上形成无空隙的外延钴硅化物（CoSi 2）层的方法。 使用HF清洁图案化的硅结构。 在图案化的硅衬底上依次形成第一钛层，钴层和第二钛层。 图案化的硅衬底在大气压下在氮气环境中在约550℃和580℃之间的温度下退火; 由此钴向下迁移并与硅结构反应以形成CoSi 2 / CoSi层，并且第一钛层向上迁移，并且第一钛层和第二钛层与硝化环境反应形成TiN。 去除TiN和未反应的钴。 将硅结构在约825℃和875℃之间的温度下退火，以将CoSi 2 / CoSi层转化为CoSi 2层。 CoSi2层可以任选地被杂质离子注入，后者被扩散以形成超浅结。

公开(公告)号：US07112866B2

公开(公告)日：2006-09-26

申请号：US10796893

申请日：2004-03-09

申请人： Lap Chan ,  Cher Liang Cha ,  Kheng Chok Tee

发明人： Lap Chan ,  Cher Liang Cha ,  Kheng Chok Tee

IPC分类号： H01L29/00 ,  H01L23/48 ,  H01L21/331 ,  H01L21/4765

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention provides a new multilevel interconnect structure of air gaps in a layer of IMD. A first layer of dielectric is provided over a surface; the surface contains metal points of contact. Trenches are provided in this first layer of dielectric. The trenches are filled with a first layer of nitride or disposable solid and polished. A second layer of dielectric is deposited over the first layer of dielectric. Trenches are formed in the second layer of dielectric, a second layer of nitride or disposable solid is deposited over the second layer of dielectric. The layer of nitride or disposable solid is polished. A thin layer of oxide is deposited over the surface of the second layer of dielectric. The thin layer of oxide is masked and etched thereby creating openings in this thin layer of oxide, these openings align with the points of intersect of the trenches in the first layer of dielectric and in the second layer of dielectric. The nitride or removable solid is removed from the trenches. The openings in the thin layer of oxide are closed off leaving a network of trenches that are filled with air in the two layers of dielectric that now function as the Inter Level Dielectric.

摘要翻译： 本发明提供了在IMD层中的空气间隙的新的多层互连结构。 在表面上提供第一层电介质; 表面含有金属接触点。 在第一层电介质中设置沟槽。 沟槽填充有第一层氮化物或一次性固体并抛光。 第二层介质沉积在第一层电介质上。 沟槽形成在第二层电介质中，第二层氮化物或一次性固体沉积在第二层电介质上。 抛光氮化物或一次性固体层。 在第二电介质层的表面上沉积薄层的氧化物。 氧化物的薄层被掩蔽和蚀刻，从而在该薄层氧化物中形成开口，这些开口与第一介电层和第二介质层中的沟槽的交叉点对准。 氮化物或可移除的固体从沟槽中去除。 氧化物薄层中的开口被封闭，留下在两层电介质中充满空气的沟槽网络，现在这两层电介质用作Inter Level Dielectric。

公开(公告)号：US07089522B2

公开(公告)日：2006-08-08

申请号：US10458992

申请日：2003-06-11

申请人： Patrick Tan ,  Kheng Chok Tee ,  David Vigar ,  Tat Wei Chua

发明人： Patrick Tan ,  Kheng Chok Tee ,  David Vigar ,  Tat Wei Chua

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  H01L21/7684 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A design, device, system and process for placing slots in active regions (e.g., metal areas). Embodiments of the present invention improve the planarization of metal areas (e.g., lines) and insulators by reducing depressions (e.g., dishing) in the metal areas by including symmetric or square slots inside selected wide metal lines, by adhering to a set of placement rules. Embodiments reduce dishing in copper dual damascene structures. Embodiments reduce data processing requirements for designing and arranging the layout of IC devices and the slots.

摘要翻译： 用于在有源区域（例如，金属区域）中放置槽的设计，装置，系统和工艺。 本发明的实施例通过通过在选定的宽金属线内包括对称或方形槽来减少金属区域中的凹陷（例如，凹陷）来改善金属区域（例如，线）和绝缘体的平坦化，通过遵守一组放置规则 。 实施例减少铜双镶嵌结构中的凹陷。 实施例减少了用于设计和布置IC器件和插槽布局的数据处理要求。

公开(公告)号：US06384437B1

公开(公告)日：2002-05-07

申请号：US09963411

申请日：2001-09-27

申请人： Kheng Chok Tee ,  Randall Cher Liang Cha ,  Lap Chan

发明人： Kheng Chok Tee ,  Randall Cher Liang Cha ,  Lap Chan

IPC分类号： H01L27148

CPC分类号： H01L27/10873 ,  H01L27/10808

摘要： Low current leakage DRAM structures are achieved using a selective silicon epitaxial growth over an insulating layer on memory cell (device) areas. An insulating layer, that also serves as a stress-release layer, and a Si3N4 hard mask are patterned to leave portions over the memory cell areas. Shallow trenches are etched in the substrate and filled with a CVD oxide which is polished back to the hard mask to form shallow trench isolation (STI) around the memory cell areas. The hard mask is selectively removed to form recesses in the STI aligned over the memory cell areas exposing the underlying insulating layer. Openings are etched in the insulating layer to provide a silicon-seed surface from which is grown a selective epitaxial layer extending over the insulating layer within the recesses. After growing a gate oxide on the epitaxial layer, FETs and DRAM capacitors can be formed on the epitaxial layer. The insulating layer under the epitaxial layer drastically reduces the capacitor leakage current and improves DRAM device performance. This self-aligning method also increases memory cell density, and is integratable into current DRAM processes to reduce cost.

摘要翻译： 使用在存储器单元（器件）区域上的绝缘层上的选择性硅外延生长来实现低电流泄漏DRAM结构。 也用作应力释放层的绝缘层和Si 3 N 4硬掩模被图案化以在存储器单元区域上留下部分。 在衬底中蚀刻浅沟槽，并填充有CVD氧化物，其被抛光回硬掩模以在存储器单元区域周围形成浅沟槽隔离（STI）。 选择性地去除硬掩模，以在STI暴露下面的绝缘层的存储单元区域上对准STI中形成凹槽。 在绝缘层中蚀刻开口以提供硅种子表面，从该晶种表面生长在凹陷内的绝缘层上延伸的选择性外延层。 在外延层上生长栅极氧化物之后，可以在外延层上形成FET和DRAM电容器。 外延层下方的绝缘层大大降低了电容器的漏电流，提高了DRAM器件性能。 这种自对准方法也增加了存储单元密度，并且可以集成到当前的DRAM工艺中以降低成本。

公开(公告)号：US06251798B1

公开(公告)日：2001-06-26

申请号：US09359894

申请日：1999-07-26

申请人： Choi Pheng Soo ,  Kheng Chok Tee ,  Kok Keng Ong ,  Lap Chan

发明人： Choi Pheng Soo ,  Kheng Chok Tee ,  Kok Keng Ong ,  Lap Chan

IPC分类号： H01L2131

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for the formation of an air gap structure for use in inter-metal applications. A metal pattern of metal lines is formed, a layer of Plasma Polymerized Methylsilane (PPMS) resist is deposited on top of this pattern. The surface of the PPMS resist is subjected to selective exposure. The unexposed PPMS is removed after which the process is completed by closing up the openings within the PPMS.

摘要翻译： 一种用于形成用于金属间应用的气隙结构的方法。 形成金属线的金属图案，在该图案的顶部上沉积一层等离子聚合甲基硅烷（PPMS）抗蚀剂。 对PPMS抗蚀剂的表面进行选择性曝光。 未曝光的PPMS被去除，之后通过关闭PPMS内的开口来完成该过程。

公开(公告)号：US07084025B2

公开(公告)日：2006-08-01

申请号：US10885855

申请日：2004-07-07

申请人： Timothy Wee Hong Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

发明人： Timothy Wee Hong Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

IPC分类号： H01L21/8238 ,  H01L21/8234 ,  H01L21/305 ,  H01L21/4763

CPC分类号： H01L29/6653 ,  H01L21/26586 ,  H01L21/28079 ,  H01L21/28123 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/66545

摘要： A process to form a FET using a replacement gate. An example feature is that the PMOS sacrificial gate is made narrower than the NMOS sacrificial gate. The PMOS gate is implanted preferably with Ge to increase the amount of poly sacrificial gate that is oxidized to form PMOS spacers. The spacers are used as masks for the LDD Implant. The space between the PLDD regions is preferably larger that the space between the NLDD regions because of the wider PMOS spacers. The PLDD tends to diffuse readily more than NLDD due to the dopant being small and light (i.e. Boron). The wider spacer between the PMOS regions improves device performance by improving the short channel effects for PMOS. In addition, the oxidization of the sacrificial gates allows trimming of sacrificial gates thus extending the limitation of lithography. Another feature of an embodiment is that a portion of the initial pad oxide is removed, thus reducing the amount of undercut created during the channel oxide strip for the dummy gate process. This would improve on the gate overlap capacitance for a T-gate transistor. In a second embodiment, two metal gates with different work functions are formed.

摘要翻译： 使用替换栅极形成FET的工艺。 一个示例特征是使PMOS牺牲栅极比NMOS牺牲栅极窄。 PMOS栅极优选用Ge注入以增加被氧化形成PMOS间隔物的多晶牺牲栅极的量。 间隔件用作LDD植入物的掩模。 PLDD区域之间的间隔优选比由于较宽的PMOS间隔物而在NLDD区域之间的间隔更大。 由于掺杂剂小且轻（即硼），PLDD容易从NLDD扩散更多。 PMOS区域之间的较宽间隔通过改善PMOS的短沟道效应来提高器件性能。 此外，牺牲栅极的氧化允许修剪牺牲栅极，从而延长了光刻的限制。 一个实施例的另一个特征是初始衬垫氧化物的一部分被去除，从而减少了在用于虚拟栅极处理的沟道氧化物带期间产生的底切的量。 这将提高T栅极晶体管的栅极重叠电容。 在第二实施例中，形成具有不同功函数的两个金属栅极。