发明授权
US06998685B2 Electrostatic discharge protection device with complementary dual drain implant
有权
具有互补双漏极植入物的静电放电保护器件
- 专利标题: Electrostatic discharge protection device with complementary dual drain implant
- 专利标题(中): 具有互补双漏极植入物的静电放电保护器件
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申请号: US10662673申请日: 2003-09-15
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公开(公告)号: US06998685B2公开(公告)日: 2006-02-14
- 发明人: Indrajit Manna , Keng Foo Lo , Pee Ya Tan , Michael Cheng
- 申请人: Indrajit Manna , Keng Foo Lo , Pee Ya Tan , Michael Cheng
- 申请人地址: SG Singapore US CA Santa Clara
- 专利权人: Chartered Semiconductor Manufacturing Ltd.,Agilent Technologies, Inc.
- 当前专利权人: Chartered Semiconductor Manufacturing Ltd.,Agilent Technologies, Inc.
- 当前专利权人地址: SG Singapore US CA Santa Clara
- 代理商 George O. Saile; Stephen B. Ackerman
- 主分类号: H01L23/62
- IPC分类号: H01L23/62
摘要:
Off-chip driver (OCD) NMOS transistors with ESD protection are formed by interposing an P-ESD implant between the N+ drain regions of OCD NMOS transistors and the N-well such that the P-ESD surrounds a section of the N-well. The P-ESD implant is dosed less than the N+ source/drain implants but higher than the N-well dose. In another embodiment, N-well doping is used along with P-ESD doping, where the P-ESD doping is chosen such that it counterdopes the N-well underneath the N+ drains. The N-well, however, still maintains electrical connection to the N+ drains. This procedure creates a larger surface under the area where the junction breakdown occurs and an increased radius of curvature of the junction. The P-ESD implant is covered by N-type on three sides creating better parasitic bipolar transistor characteristics.
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