公开(公告)号：US06998685B2

公开(公告)日：2006-02-14

申请号：US10662673

申请日：2003-09-15

申请人： Indrajit Manna ,  Keng Foo Lo ,  Pee Ya Tan ,  Michael Cheng

发明人： Indrajit Manna ,  Keng Foo Lo ,  Pee Ya Tan ,  Michael Cheng

IPC分类号： H01L23/62

CPC分类号： H01L29/0847 ,  H01L27/0266 ,  H01L29/1083 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： Off-chip driver (OCD) NMOS transistors with ESD protection are formed by interposing an P-ESD implant between the N+ drain regions of OCD NMOS transistors and the N-well such that the P-ESD surrounds a section of the N-well. The P-ESD implant is dosed less than the N+ source/drain implants but higher than the N-well dose. In another embodiment, N-well doping is used along with P-ESD doping, where the P-ESD doping is chosen such that it counterdopes the N-well underneath the N+ drains. The N-well, however, still maintains electrical connection to the N+ drains. This procedure creates a larger surface under the area where the junction breakdown occurs and an increased radius of curvature of the junction. The P-ESD implant is covered by N-type on three sides creating better parasitic bipolar transistor characteristics.

摘要翻译： 具有ESD保护的片外驱动器（OCD）NMOS晶体管通过在OCD NMOS晶体管的N +漏极区域和N阱之间插入P-ESD注入而形成，使得P-ESD围绕N阱的一部分。 P-ESD植入物的剂量小于N +源/漏植入物，但高于N阱剂量。 在另一个实施例中，使用N阱掺杂以及P-ESD掺杂，其中选择P-ESD掺杂使得其对N +漏极下方的N阱进行反向。 然而，N阱仍然保持与N +排水管的电气连接。 该过程在结点发生的区域下面形成较大的表面，并且连接部的曲率半径增加。 P-ESD植入体在三面覆盖N型，产生更好的寄生双极晶体管特性。

公开(公告)号：US06936895B2

公开(公告)日：2005-08-30

申请号：US10682055

申请日：2003-10-09

申请人： Indrajit Manna ,  Keng Foo Lo ,  Pee Ya Tan ,  Raymond Filippi

发明人： Indrajit Manna ,  Keng Foo Lo ,  Pee Ya Tan ,  Raymond Filippi

IPC分类号： H01L21/425 ,  H01L21/8234 ,  H01L23/62 ,  H01L27/02 ,  H01L29/49 ,  H01L29/868 ,  H01L31/075

CPC分类号： H01L29/4983 ,  H01L27/0255 ,  H01L27/0266 ,  H01L29/868 ,  H01L2924/0002 ,  H01L2924/00

摘要： A new method to form an integrated circuit device is achieved. The method comprises forming a dielectric layer overlying a semiconductor substrate. An intrinsic semiconductor layer is formed overlying the dielectric layer. The intrinsic semiconductor layer is patterned. A p+ region is formed in the intrinsic semiconductor layer. An n+ region is formed in the intrinsic semiconductor layer. The p+ region and said n+ region are laterally separated by an intrinsic region to thereby form a PIN diode device. A source region and a drain region are formed in the semiconductor substrate to thereby complete a MOSFET device. The PIN diode device is a gate electrode for the MOSFET device.

摘要翻译： 实现了形成集成电路器件的新方法。 该方法包括形成覆盖半导体衬底的电介质层。 形成覆盖在介电层上的本征半导体层。 本征半导体层被图案化。 在本征半导体层中形成p +区。 在本征半导体层中形成n +区。 p +区域和所述n +区域被本征区域横向分开，从而形成PIN二极管器件。 在半导体衬底中形成源极区和漏极区，从而完成MOSFET器件。 PIN二极管器件是用于MOSFET器件的栅电极。

公开(公告)号：US07135743B2

公开(公告)日：2006-11-14

申请号：US11291757

申请日：2005-12-01

申请人： Indrajit Manna ,  Keng Foo Lo ,  Pee Ya Tan ,  Michael Cheng

发明人： Indrajit Manna ,  Keng Foo Lo ,  Pee Ya Tan ,  Michael Cheng

IPC分类号： H01L23/62

CPC分类号： H01L29/0847 ,  H01L27/0266 ,  H01L29/1083 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： Off-chip driver (OCD) NMOS transistors with ESD protection are formed by interposing an P-ESD implant between the N+ drain regions of OCD NMOS transistors and the N-well such that the P-ESD surrounds a section of the N-well. The P-ESD implant is dosed less than the N+ source/drain implants but higher than the N-well dose. In another embodiment, N-well doping is used along with P-ESD doping, where the P-ESD doping is chosen such that it counterdopes the N-well underneath the N+ drains. The N-well, however, still maintains electrical connection to the N+ drains. This procedure creates a larger surface under the area where the junction breakdown occurs and an increased radius of curvature of the junction. The P-ESD implant is covered by N-type on three sides creating better parasitic bipolar transistor characteristics.

公开(公告)号：US06835985B2

公开(公告)日：2004-12-28

申请号：US09733836

申请日：2000-12-09

申请人： Jun Cai ,  Guang Ping Hua ,  Jun Song ,  Keng Foo Lo

发明人： Jun Cai ,  Guang Ping Hua ,  Jun Song ,  Keng Foo Lo

IPC分类号： H01L2362

CPC分类号： H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor structure is provided for ESD protection in an integrated circuit device. A semiconductor substrate has source and drain diffusion regions and respective source and drain wells under the source and drain diffusion regions. A shallow trench isolation formed over the semiconductor substrate and into the semiconductor substrate separates the source and drain diffusion regions and a portion of the source and drain wells. Source and drain contact structures respectively formed on the shallow trench isolation over the source and drain diffusion regions and extend through the shallow trench isolation to contact the source and drain diffusion regions. An ion implantation is performed through the contact openings into the bottoms of the source and drain wells to control the device trigger voltage and position the discharge current far away from the surface, which increases the device ESD performance significantly.

公开(公告)号：US06265251B1

公开(公告)日：2001-07-24

申请号：US09566471

申请日：2000-05-08

申请人： Cai Jun ,  Keng Foo Lo

发明人： Cai Jun ,  Keng Foo Lo

IPC分类号： H01L21338

CPC分类号： H01L29/6659 ,  H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

摘要： A new method of forming a thick oxide MOS transistor for electrostatic discharge protection in a standard sub-micron STI CMOS process for an integrated circuit device has been achieved. A first well and a second well are implanted. The wells are counter-doped to the substrate type. The first well forms the drain, and the second well forms the source. A thin oxide layer is formed. A polysilicon layer is deposited. The polysilicon layer is patterned to form a dummy floating gate. Ions are implanted into the first well to form a first lightly-doped region and into the second well to form a second lightly-doped region of the same type as the wells. The lightly-doped regions are self-aligned to the dummy floating gate. Sidewall spacers are formed on the floating dummy gates. Ions are implanted into the first well to form a first heavily-doped region and the second well to to form a second heavily-doped region of the same type as the wells. The heavily-doped regions are self-aligned to the sidewall spacers. An interlevel dielectric layer is deposited. A metal layer is deposited overlying the interlevel dielectric layer. The metal layer is patterned to form the gate electrode.

摘要翻译： 已经实现了在用于集成电路器件的标准亚微米STI CMOS工艺中形成用于静电放电保护的厚氧化物MOS晶体管的新方法。 植入第一口井和第二口井。 这些阱被反掺杂到衬底类型。 第一口井形成排水沟，第二口井形成排水沟。 形成薄的氧化物层。 沉积多晶硅层。 图案化多晶硅层以形成虚拟浮动栅极。 将离子注入到第一阱中以形成第一轻掺杂区域并进入第二阱以形成与孔相同类型的第二轻掺杂区域。 轻掺杂区域与虚拟浮栅自对准。 侧壁间隔件形成在浮动虚拟门上。 将离子注入到第一阱中以形成第一重掺杂区，而第二阱形成与阱相同类型的第二重掺杂区。 重掺杂区域与侧壁间隔物自对准。 沉积层间电介质层。 沉积层叠介质层上的金属层。 图案化金属层以形成栅电极。

公开(公告)号：US09165920B2

公开(公告)日：2015-10-20

申请号：US11163349

申请日：2005-10-15

申请人： Indrajit Manna ,  Hin Kiong Yap ,  Keng Foo Lo ,  Jae Soo Park

发明人： Indrajit Manna ,  Hin Kiong Yap ,  Keng Foo Lo ,  Jae Soo Park

IPC分类号： H01L29/66 ,  H01L23/62 ,  H01L29/02 ,  H01L29/06 ,  H01L23/58 ,  H01L27/02

CPC分类号： H01L27/0262 ,  H01L29/7436 ,  H01L2924/0002 ,  H01L2924/00

摘要： A tunable protection system including forming a tunable trigger device providing an adjustable protection activation level, forming a circuit protection device providing protection for integrated circuits, and electrically connecting the tunable trigger device and the circuit protection device to an input/output pad.

摘要翻译： 一种可调谐保护系统，包括形成提供可调保护激活电平的可调谐触发装置，形成为集成电路提供保护的电路保护装置，以及将可调谐触发装置和电路保护装置电连接到输入/输出垫。

公开(公告)号：US07064358B2

公开(公告)日：2006-06-20

申请号：US10743596

申请日：2003-12-22

申请人： Indrajlt Manna ,  Keng Foo Lo ,  Pee Ya Tan ,  Raymond Filippi

发明人： Indrajlt Manna ,  Keng Foo Lo ,  Pee Ya Tan ,  Raymond Filippi

IPC分类号： H01L29/72

CPC分类号： H01L27/0259

摘要： An embodiment is a Electro Static Discharge (ESD) protection device comprising: a n-doped region and a p-doped region in a p-well in a semiconductor structure. The n-doped region and the p-doped region are spaced. A n-well and a deep n-well surrounding the p-well on the sides and bottom. A first I/O pad connected to the n-doped region. A trigger circuit connected the first I/O pad and the p-doped region. A second I/O pad connected to the n-well. A parasitic bipolar transistor is comprised of the n-doped region that functions as a collector terminal, the P-well that functions as a base terminal, and the deep N-well that functions as the emitter terminal. Whereby under an ESD condition, the p-well is charged positive using the trigger circuit and the parasitic bipolar transistor can be turned on.

摘要翻译： 一个实施例是一种静电放电（ESD）保护装置，其包括：半导体结构中的p阱中的n掺杂区域和p掺杂区域。 n掺杂区域和p掺杂区域间隔开。 围绕p-well的两侧和底部的n井和深n井。 连接到n掺杂区域的第一I / O焊盘。 连接第一I / O焊盘和p掺杂区域的触发电路。 连接到n阱的第二个I / O焊盘。 寄生双极晶体管由用作集电极端子的n掺杂区域，用作基极端子的P阱和用作发射极端子的深N阱组成。 在ESD条件下，使用触发电路将p阱充电为正极，并且可以接通寄生双极晶体管。

公开(公告)号：US06855609B2

公开(公告)日：2005-02-15

申请号：US10670918

申请日：2003-09-24

申请人： Jun Cai ,  Guang Ping Hua ,  Jun Song ,  Keng Foo Lo

发明人： Jun Cai ,  Guang Ping Hua ,  Jun Song ,  Keng Foo Lo

IPC分类号： H01L27/02 ,  H01L21/336

CPC分类号： H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor structure is manufactured for ESD protection in an integrated circuit device. A semiconductor substrate has source and drain diffusion regions and respective source and drain wells under the source and drain diffusion regions. A shallow trench isolation formed over the semiconductor substrate and into the semiconductor substrate separates the source and drain diffusion regions and a portion of the source and drain wells. Source and drain contact structures respectively formed on the shallow trench isolation over the source and drain diffusion regions and extend through the shallow trench isolation to contact the source and drain diffusion regions. An ion implantation is performed through the contact openings into the bottoms of the source and drain wells to control the device trigger voltage and position the discharge current far away from the surface, which increases the device ESD performance significantly.

摘要翻译： 在集成电路器件中制造用于ESD保护的晶体管结构。 半导体衬底具有源极和漏极扩散区域以及源极和漏极扩散区域下的源极和漏极阱。 形成在半导体衬底上并进入半导体衬底的浅沟槽隔离件分离源极和漏极扩散区域以及源极和漏极阱的一部分。 源极和漏极接触结构分别形成在源极和漏极扩散区上的浅沟槽隔离上，并延伸穿过浅沟槽隔离以接触源极和漏极扩散区域。 通过接触开口进入离子注入到源阱和漏极的底部，以控制器件触发电压并将放电电流定位远离表面，从而显着提高器件ESD性能。

公开(公告)号：US06310380B1

公开(公告)日：2001-10-30

申请号：US09519838

申请日：2000-03-06

申请人： Jun Cai ,  Keng Foo Lo

发明人： Jun Cai ,  Keng Foo Lo

IPC分类号： H01L2362

CPC分类号： H01L29/0847 ,  H01L27/0277 ,  H01L29/0653 ,  H01L29/456 ,  H01L29/7833

摘要： A MOS transistor structure is provided for ESD protection in an integrated circuit device. A trench controls salicide deposition to prevent hot spot formation and allows control of the turn-on voltage. The structure includes source and drain diffusion regions formed in the silicon substrate, a gate, and n-wells formed under the source and drain diffusions on either side of the gate. A drain trench is located to separate the salicide between a drain contact and the gate edge, and by controlling the size and location of the drain trench, the turn-on voltages can be controlled; i.e., the turn-on voltage due to drain diffusion region to substrate avalanche breakdown and the turn-on voltage due to source well to drain well punch-through. Thus, very low turn-on voltages may be achieved for ESD protection.

摘要翻译： 在集成电路器件中提供用于ESD保护的MOS晶体管结构。 沟槽控制硅化物沉积以防止热点形成并且允许控制导通电压。 该结构包括在硅衬底中形成的源极和漏极扩散区域，栅极和形成在栅极两侧的源极和漏极扩散之下的n阱。 漏极沟槽被定位成在漏极接触和栅极边缘之间分离硅化物，并且通过控制漏极沟槽的尺寸和位置，可以控制导通电压; 即由于漏极扩散区域到衬底雪崩击穿引起的导通电压以及由于源极而导致漏极穿透的导通电压。 因此，ESD保护可以实现非常低的导通电压。

公开(公告)号：US07205612B2

公开(公告)日：2007-04-17

申请号：US10978627

申请日：2004-11-01

申请人： Jun Cai ,  Keng Foo Lo

发明人： Jun Cai ,  Keng Foo Lo

IPC分类号： H01L23/62 ,  H01L29/72 ,  H01L29/74 ,  H01L31/111 ,  H01L31/119

CPC分类号： H01L29/0847 ,  H01L27/0266 ,  H01L29/1083 ,  H01L29/7833 ,  Y10S257/90

摘要： A device and method are described for forming a grounded gate NMOS (GGNMOS) device used to provide protection against electrostatic discharge (ESD) in an integrated circuit (IC). The device is achieved by adding n-wells below the source and drain regions. By tailoring the dopant concentration profiles of the p-well and n-wells provided in the fabrication process, peak dopant concentrations are moved below the silicon surface. This moves ESD conduction deeper into the IC where thermal conductivity is improved, thereby avoiding thermal damage occurring with surface conduction. The device does not require a salicidation block or additional implantation and uses standard NMOS fabrication processing steps, making it advantageous over prior art solutions.

摘要翻译： 描述了用于形成用于提供集成电路（IC）中的静电放电（ESD）保护的接地栅极NMOS（GGNMOS）器件的器件和方法。 该器件通过在源极和漏极区域下方添加n阱来实现。 通过调整在制造过程中提供的p阱和n阱的掺杂浓度分布，峰值掺杂剂浓度移动到硅表面以下。 这将ESD传导更深地传导到IC中，其中导热性得到改善，从而避免了表面传导引起的热损伤。 该器件不需要一个盐化阻滞或额外的植入，并且使用标准的NMOS制造处理步骤，使其优于现有技术的解决方案。