发明授权
- 专利标题： Low stress sidewall spacer in integrated circuit technology
- 专利标题（中）： 集成电路技术中的低应力侧壁间隔
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申请号： US10756023申请日： 2004-01-12
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公开(公告)号： US07005357B2公开(公告)日： 2006-02-28
- 发明人: Minh Van Ngo , Simon Siu-Sing Chan , Paul R. Besser , Paul L. King , Errol Todd Ryan , Robert J. Chiu
- 申请人： Minh Van Ngo , Simon Siu-Sing Chan , Paul R. Besser , Paul L. King , Errol Todd Ryan , Robert J. Chiu
- 申请人地址： US CA Sunnyvale
- 专利权人： Advanced Micro Devices, Inc.
- 当前专利权人： Advanced Micro Devices, Inc.
- 当前专利权人地址： US CA Sunnyvale
- 代理商 Mikio Ishimaru
- 主分类号： H01L21/336
- IPC分类号： H01L21/336 ; H01L21/441
摘要：
A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate using a low power plasma enhanced chemical vapor deposition process A silicide is formed on the source/drain junctions and on the gate, and an interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.
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