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    Low stress sidewall spacer in integrated circuit technology
    1.
    发明授权
    Low stress sidewall spacer in integrated circuit technology 有权
    集成电路技术中的低应力侧壁间隔

    公开(公告)号：US07005357B2

    公开(公告)日：2006-02-28

    申请号：US10756023

    申请日：2004-01-12

    申请人： Minh Van Ngo ,  Simon Siu-Sing Chan ,  Paul R. Besser ,  Paul L. King ,  Errol Todd Ryan ,  Robert J. Chiu

    发明人： Minh Van Ngo ,  Simon Siu-Sing Chan ,  Paul R. Besser ,  Paul L. King ,  Errol Todd Ryan ,  Robert J. Chiu

    IPC分类号： H01L21/336 ,  H01L21/441

    CPC分类号： H01L29/6659 ,  H01L29/665

    摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate using a low power plasma enhanced chemical vapor deposition process A silicide is formed on the source/drain junctions and on the gate, and an interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.

    摘要翻译： 提供一种形成具有半导体衬底的集成电路的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 使用低功率等离子体增强化学气相沉积工艺在栅极周围形成侧壁间隔物。在源极/漏极结和栅极上形成硅化物，并且在半导体衬底上沉积层间电介质。 然后在层间电介质中形成与硅化物的接触。

    Method of manufacturing a semiconductor device with reliable contacts/vias
    2.
    发明授权
    Method of manufacturing a semiconductor device with reliable contacts/vias 有权
    制造具有可靠接触/通孔的半导体器件的方法

    公开(公告)号：US06576548B1

    公开(公告)日：2003-06-10

    申请号：US10079861

    申请日：2002-02-22

    申请人： Amy Tu ,  Minh Van Ngo ,  Austin Frenkel ,  Robert J. Chiu ,  Jeff Erhardt

    发明人： Amy Tu ,  Minh Van Ngo ,  Austin Frenkel ,  Robert J. Chiu ,  Jeff Erhardt

    IPC分类号： H01L214763

    CPC分类号： H01L21/76843 ,  H01L21/31105 ,  H01L21/76804 ,  H01L21/76846 ,  H01L21/76877

    摘要： Reliable contacts/vias are formed by sputter etching to flare exposed edges of an opening formed in a dielectric layer, depositing a composite barrier layer and then filling the opening with tungsten at a low deposition rate. The resulting contact/via exhibits significantly reduced porosity and contact resistance. Embodiments include sputter etching to incline the edges of an opening formed in an oxide dielectric layer, e.g., a silicon oxide derived from TEOS or BPSG, at an angle of about 83° to about 86°, depositing a thin layer of Ti, e.g., at a thickness of about 250 Å to about 350 Å, depositing at least one layer of titanium nitride, e.g., three layers of titanium nitride, at a total thickness of about 130 Å to about 170 Å, and then depositing tungsten at a deposition rate of about 1,900 to about 2,300 Å/min to fill the opening.

    摘要翻译： 通过溅射蚀刻形成可靠的触点/通孔，以对形成在电介质层中的开口的暴露边缘进行曝光，沉积复合阻挡层，然后以低沉积速率用钨填充开口。 所得到的接触/通孔显示出显着降低的孔隙率和接触电阻。 实施例包括溅射蚀刻，以约83°至约86°的角度倾斜形成在氧化物电介质层中的开口的边缘，例如衍生自TEOS或BPSG的氧化硅，沉积Ti薄层， 在约250埃至大约350埃的厚度上沉积至少一层氮化钛，例如三层氮化钛，总厚度为约至约为170埃，然后以沉积速率沉积钨 约1,900至约2,300埃/分钟以填充开口。

    Low cost application of oxide test wafer for defect monitor in photolithography process
    3.
    发明授权
    Low cost application of oxide test wafer for defect monitor in photolithography process 失效
    用于光刻工艺中缺陷监测器的氧化物测试晶片的低成本应用

    公开(公告)号：US06171737B2

    公开(公告)日：2001-01-09

    申请号：US09017695

    申请日：1998-02-03

    申请人： Khoi A. Phan ,  Shobhana R. Punjabi ,  Robert J. Chiu ,  Bhanwar Singh

    发明人： Khoi A. Phan ,  Shobhana R. Punjabi ,  Robert J. Chiu ,  Bhanwar Singh

    IPC分类号： G03F900

    CPC分类号： G03F7/7065 ,  H01L22/20 ,  H01L22/34

    摘要： A low cost technique for detecting defects in photolithography processes in a submicron integrated circuit manufacturing environment combines use of a reusable test wafer with in-line processing to monitor defects using a pattern comparator system. A reusable test wafer having an oxide layer overlying a silicon substrate and having a thickness corresponding to a minimum reflectance for an exposure wavelength used for photolithography is patterned using a prescribed photolithographic fabrication process to form a repetitive pattern according to a prescribed design product rule. The pattern is formed using a reticle having a repetitive pattern array with a similar design rule as the product to be developed by the lithography processes. The patterned test wafer is then inspected using image-based inspection techniques, where the image has high resolution pixels of preferably 0.25 microns per pixel. An optical review station and scanning electron microscope system are used to review defect and classify defect types. The test wafer can then be reused by cleaning the photolithographic pattern by removing the photoresist, and then removing polymer particles adhering to the oxide layer following removal of the photoresist.

    摘要翻译： 在亚微米集成电路制造环境中用于检测光刻工艺中的缺陷的低成本技术将使用可重复使用的测试晶片与在线处理相结合，以使用模式比较器系统来监测缺陷。 使用规定的光刻制造工艺对具有覆盖在硅衬底上并具有与用于光刻的曝光波长的最小反射率相对应的厚度的可重复使用的测试晶片图案化以根据规定的设计产品规则形成重复图案。 使用具有与通过光刻工艺开发的产品相似的设计规则的具有重复图案阵列的掩模版形成图案。 然后使用基于图像的检查技术来检查图案化的测试晶片，其中图像具有每像素优选0.25微米的高分辨率像素。 光学检查站和扫描电子显微镜系统用于检查缺陷并分类缺陷类型。 然后可以通过除去光致抗蚀剂来清洁光刻图案，然后在去除光致抗蚀剂之后去除粘附到氧化物层上的聚合物颗粒，来重新使用测试晶片。

    Ultra-uniform silicide system in integrated circuit technology
    6.
    发明授权
    Ultra-uniform silicide system in integrated circuit technology 有权
    集成电路技术中超均匀的硅化物系统

    公开(公告)号：US07307322B2

    公开(公告)日：2007-12-11

    申请号：US11252493

    申请日：2005-10-17

    申请人： Robert J. Chiu ,  Jeffrey P. Patton ,  Paul R. Besser ,  Minh Van Ngo

    发明人： Robert J. Chiu ,  Jeffrey P. Patton ,  Paul R. Besser ,  Minh Van Ngo

    IPC分类号： H01L29/76

    CPC分类号： H01L21/28518

    摘要： A structure of an integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform suicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.

    摘要翻译： 提供集成电路的结构。 在半导体衬底上形成栅极电介质，并且在半导体衬底上的栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 在源极/漏极结上形成超均匀的硅化物，并且在半导体衬底上沉积电介质层。 然后在介电层中形成与超均匀硅化物的接触。

    Ultra-uniform silicides in integrated circuit technology
    8.
    发明授权
    Ultra-uniform silicides in integrated circuit technology 有权
    集成电路技术中超均匀的硅化物

    公开(公告)号：US07005376B2

    公开(公告)日：2006-02-28

    申请号：US10615086

    申请日：2003-07-07

    申请人： Robert J. Chiu ,  Jeffrey P. Patton ,  Paul R. Besser ,  Minh Van Ngo

    发明人： Robert J. Chiu ,  Jeffrey P. Patton ,  Paul R. Besser ,  Minh Van Ngo

    IPC分类号： H01L21/00

    CPC分类号： H01L21/28518

    摘要： A method of forming and a structure of an integrated circuit are provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform silicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.

    摘要翻译： 提供一种集成电路的形成方法和结构。 在半导体衬底上形成栅极电介质，并且在半导体衬底上的栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 在源极/漏极结上形成超均匀的硅化物，并且在半导体衬底上沉积电介质层。 然后在电介质层中形成与超均匀硅化物的接触。

    Contact liner in integrated circuit technology
    9.
    发明授权
    Contact liner in integrated circuit technology 有权
    接触式衬板集成电路技术

    公开(公告)号：US07670915B1

    公开(公告)日：2010-03-02

    申请号：US10791096

    申请日：2004-03-01

    申请人： Errol Todd Ryan ,  Paul R. Besser ,  Simon Siu-Sing Chan ,  Robert J. Chiu ,  Mehrdad Mahanpour ,  Minh Van Ngo

    发明人： Errol Todd Ryan ,  Paul R. Besser ,  Simon Siu-Sing Chan ,  Robert J. Chiu ,  Mehrdad Mahanpour ,  Minh Van Ngo

    IPC分类号： H01L21/20

    CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L29/7833

    摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain junctions and on the gate. An interlayer dielectric having contact holes therein is formed above the semiconductor substrate. Contact liners are formed in the contact holes, and contacts are then formed over the contact liners. The contact liners are nitrides of the contact material, and formed at a temperature below the thermal budget for the silicide.

    摘要翻译： 提供一种形成具有半导体衬底的集成电路的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 在源极/漏极结和栅极上形成硅化物。 在半导体衬底的上方形成有具有接触孔的层间电介质。 接触衬垫形成在接触孔中，然后在接触衬垫上形成接触。 接触衬垫是接触材料的氮化物，并且在低于硅化物的热预算的温度下形成。

    PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING DEPOSITING LAYERS WITHIN OPENINGS
    10.
    发明申请
    PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING DEPOSITING LAYERS WITHIN OPENINGS 审中-公开
    形成电子器件的方法，包括开孔中的沉积层

    公开(公告)号：US20090050471A1

    公开(公告)日：2009-02-26

    申请号：US11844518

    申请日：2007-08-24

    申请人： Robert J. Chiu ,  Connie Pin-Chin Wang ,  Minh Van Ngo ,  Simon S. Chan

    发明人： Robert J. Chiu ,  Connie Pin-Chin Wang ,  Minh Van Ngo ,  Simon S. Chan

    IPC分类号： C23C14/32

    CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76814 ,  H01L23/485

    摘要： A process of forming an electronic device can include depositing a first layer over a substrate and depositing a second layer over the first layer. In one embodiment, depositing the first layer is performed at a first alternating current (“AC”) power, and depositing the second layer is performed at a second AC power that is different from the first AC power. In another embodiment, the first layer is formed by a physical vapor deposition technique at a first power sufficient to remove the insulating layer using first metal ions, wherein the first layer includes an overhanging portion extending over the bottom of the opening. In a further embodiment, the second layer is formed by the physical vapor deposition technique using second metal ions and a second power sufficient to reduce a lateral dimension of the overhanging portion.

    摘要翻译： 形成电子器件的过程可以包括在衬底上沉积第一层并在第一层上沉积第二层。 在一个实施例中，在第一交流（“AC”）功率下执行沉积第一层，并且以不同于第一AC电力的第二AC电源执行沉积第二层。 在另一个实施例中，第一层通过物理气相沉积技术以足以使用第一金属离子去除绝缘层的第一功率形成，其中第一层包括在开口底部延伸的伸出部分。 在另一个实施例中，第二层通过使用第二金属离子的物理气相沉积技术和足以减少突出部分的横向尺寸的第二功率形成。