发明授权
US07005939B2 Input/output circuit with on-chip inductor to reduce parasitic capacitance
有权
具有片上电感的输入/输出电路，以减少寄生电容
- 专利标题： Input/output circuit with on-chip inductor to reduce parasitic capacitance
- 专利标题（中）： 具有片上电感的输入/输出电路，以减少寄生电容
-
申请号： US10431147申请日： 2003-05-06
-
公开(公告)号： US07005939B2公开(公告)日： 2006-02-28
- 发明人: Jared L. Zerbe , Vladimir M. Stojanovic , Mark A. Horowitz , Pak S. Chau
- 申请人： Jared L. Zerbe , Vladimir M. Stojanovic , Mark A. Horowitz , Pak S. Chau
- 申请人地址： US CA Los Altos
- 专利权人： Rambus Inc.
- 当前专利权人： Rambus Inc.
- 当前专利权人地址： US CA Los Altos
- 代理机构： Vierra Magen Marcus Harmon & DeNiro LLP
- 主分类号： H01P5/12
- IPC分类号： H01P5/12
摘要：
An I/O circuit disposed on an integrated circuit substrate and having reduced parasitic capacitance. The I/O circuit includes a signal line segmented into a first signal line segment and a second signal line segment, and an inductive structure disposed between the first and second signal line segments. An on-chip termination element is coupled to the first signal line segment, and an electrostatic discharge (ESD) element is coupled to the second signal line segment.
公开/授权文献
信息查询
