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    Connector with integral transmission line bus
    1.
    再颁专利
    Connector with integral transmission line bus 有权
    带集成传输线总线的连接器

    公开(公告)号：USRE39153E1

    公开(公告)日：2006-07-04

    申请号：US09871313

    申请日：2001-05-31

    申请人： Donald V. Perino ,  James A. Gasbarro ,  Nancy David Dillon

    发明人： John B. Dillon

    IPC分类号： H01R9/00

    CPC分类号： H01R12/7076 ,  H01R12/712 ,  H01R13/658

    摘要： A socket (14) includes a first bus conductor (22a) having two or more contact regions (24) and a second bus conductor (22b) arranged substantially parallel to the first bus conductor and having two or more contact regions (24). The first and second bus conductors are spaced relative to one another so as to provide a predetermined electrical impedance and may be arranged to carry electrical signals as transmission lines. A dielectric spacer (36) may be disposed between the first and second bus conductors to provide the spacing. Contact regions (24) of the first and second conductors (22a, 22b) may provide compliant coupling regions for the socket (14). The contact regions (24) of the first bus conductor (22a) may be positioned within the socket (14) so as to contact a lead disposed on a first side of a circuit element (16) and the contact regions (24) of the second bus conductor (22b) may be positioned within the socket (14) so as to contact the lead disposed on the second side of the circuit element (16).

    摘要翻译： 插座（14）包括具有两个或多个接触区域（24）的第一总线导体（22a）和基本上平行于第一总线导体布置并具有两个或多个接触区域（24）的第二总线导体（22b） 。 第一和第二总线导体相对于彼此间隔开以提供预定的电阻抗，并且可以被布置为承载作为传输线的电信号。 电介质间隔物（36）可以设置在第一和第二总线导体之间以提供间隔。 第一和第二导体（22a，22b）的接触区域（24）可以为插座（14）提供顺应的耦合区域。 第一总线导体（22a）的接触区域（24）可以定位在插座（14）内，以便接触设置在电路元件（16）的第一侧上的引线和接触区域（24）的接触区域 第二总线导体（22b）可以定位在插座（14）内，以便接触设置在电路元件（16）的第二侧上的引线。

    System and method featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices
    4.
    发明授权
    System and method featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices 失效
    具有控制器装置和存储模块的系统和方法包括集成电路缓冲装置和多个集成电路存储装置

    公开(公告)号：US07000062B2

    公开(公告)日：2006-02-14

    申请号：US11054797

    申请日：2005-02-10

    申请人： Richard E. Perego ,  Stefanos Sidiropoulos ,  Ely Tsern

    发明人： Richard E. Perego ,  Stefanos Sidiropoulos ,  Ely Tsern

    IPC分类号： G06F12/00

    CPC分类号： G11C29/028 ,  G06F13/1673 ,  G06F13/1684 ,  G11C5/04 ,  G11C7/10 ,  G11C29/02 ,  G11C29/50012

    摘要： A system comprises a master device and a first integrated circuit buffer device. A first plurality of integrated circuit memory devices are coupled to the first integrated circuit buffer device. A first plurality of signal lines are coupled to the first integrated circuit buffer device and the master device, wherein the first plurality of signal lines communicate control information, address information and data from the master device to the first integrated circuit buffer device. A second plurality of signal lines are coupled to the first integrated circuit buffer device. A second integrated circuit buffer device is coupled to the second plurality of signal lines, the second integrated circuit buffer device receives the control information, the address information and the data from the first integrated circuit buffer device over the second plurality of signal lines. A second plurality of integrated circuit memory devices are coupled to the second integrated circuit buffer device. A third plurality of signal lines are coupled to the first integrated circuit buffer device, the second integrated circuit buffer device and the master device. The third plurality of signal lines communicate information from the master device that initialize the first integrated circuit buffer device and the second integrated circuit buffer device.

    摘要翻译： 系统包括主设备和第一集成电路缓冲设备。 第一组多个集成电路存储器件耦合到第一集成电路缓冲器件。 第一多个信号线耦合到第一集成电路缓冲器装置和主装置，其中第一多个信号线将控制信息，地址信息和数据从主装置传送到第一集成电路缓冲装置。 第二组多个信号线耦合到第一集成电路缓冲器件。 第二集成电路缓冲器件耦合到第二多个信号线，第二集成电路缓冲器件通过第二多个信号线从第一集成电路缓冲器件接收控制信息，地址信息和数据。 第二组多个集成电路存储器件耦合到第二集成电路缓冲器件。 第三组信号线耦合到第一集成电路缓冲器件，第二集成电路缓冲器件和主器件。 第三多个信号线传送来自初始化第一集成电路缓冲装置和第二集成电路缓冲装置的主装置的信息。

    Clock alignment circuit having a self regulating voltage supply
    6.
    发明授权
    Clock alignment circuit having a self regulating voltage supply 失效
    具有自调节电压源的时钟对准电路

    公开(公告)号：US06928128B1

    公开(公告)日：2005-08-09

    申请号：US09303669

    申请日：1999-05-03

    申请人： Stefanos Sidiropoulos

    发明人： Stefanos Sidiropoulos

    IPC分类号： H03D3/24 ,  H03K5/00 ,  H03K5/13 ,  H03L7/081 ,  H03L7/089

    CPC分类号： H03L7/0812 ,  H03K5/133 ,  H03K2005/00026 ,  H03L7/0896

    摘要： Clock alignment circuits and techniques for reducing power dissipation, increasing power supply noise immunity, decreasing process and temperature variation sensitivity, and providing a wide operating range. A power supply generator generates an isolated supply voltage for a delay line used in a clock alignment circuit. The delay line generates a delayed clock from a reference clock. A comparator detects a correction information (i.e., delay or phase error) between the delayed clock and the reference clock and generates error information representative of the correction information. A charge pump circuit converts the error information into a voltage signal, wherein the voltage signal is a scaled representation of the error information. The power supply generator includes an amplifier having a first input coupled to the voltage signal and an output to provide the supply voltage and a capacitor coupled between the supply voltage and a ground voltage, wherein the amplifier tracks the voltage signal level to regulate the supply voltage.

    摘要翻译： 用于降低功耗的时钟对准电路和技术，提高电源噪声抗扰度，降低工艺和温度变化灵敏度，并提供广泛的工作范围。 电源发生器为时钟对准电路中使用的延迟线产生隔离电源电压。 延迟线从参考时钟产生延迟时钟。 比较器检测延迟时钟和参考时钟之间的校正信息（即，延迟或相位误差），并产生表示校正信息的误差信息。 电荷泵电路将误差信息转换成电压信号，其中电压信号是误差信息的缩放表示。 电源发生器包括具有耦合到电压信号的第一输入和提供电源电压的输出和耦合在电源电压和接地电压之间的电容器的放大器，其中放大器跟踪电压信号电平以调节电源电压 。

    Memory device which receives write masking information
    7.
    发明授权
    Memory device which receives write masking information 失效
    接收写入掩蔽信息的存储器件

    公开(公告)号：US06912620B2

    公开(公告)日：2005-06-28

    申请号：US10686318

    申请日：2003-10-15

    申请人： Frederick Abbott Ware ,  Craig Edward Hampel ,  Donald Charles Stark ,  Matthew Murdy Griffin

    发明人： Frederick Abbott Ware ,  Craig Edward Hampel ,  Donald Charles Stark ,  Matthew Murdy Griffin

    IPC分类号： G11C11/413 ,  G11C7/22 ,  G11C11/401 ,  G06F12/00

    CPC分类号： G11C7/22

    摘要： A method is described for providing a memory with a serial sequence of write enable signals that are offset in time with respect to respective data received by a plurality of data inputs of the memory. A memory is also described with an array for data storage, a plurality of data input pins, and a separate pin for receiving either additional data or a serial sequence of write enable signals applicable to data received by the plurality of data input pins. The additional data that the separate pin can receive includes, for example, error detection and correction (EDC) information. A method is also described for multiplexing write enable information and error detection and correction information.

    摘要翻译： 描述了一种用于向存储器提供相对于由存储器的多个数据输入接收的相应数据在时间上偏移的写使能信号的串行序列的存储器。 还描述了一种用于数据存储的阵列，多个数据输入引脚和用于接收适用于由多个数据输入引脚接收的数据的附加数据或可写入使能信号的串行序列的单独引脚的存储器。 单独引脚可以接收的附加数据包括例如错误检测和校正（EDC）信息。 还描述了一种用于复用写使能信息和错误检测和校正信息的方法。

    Method, system and computer readable medium for providing an output signal having a theme to a device in a short distance wireless network
    9.
    发明授权
    Method, system and computer readable medium for providing an output signal having a theme to a device in a short distance wireless network 失效
    用于向短距离无线网络中的设备提供具有主题的输出信号的方法，系统和计算机可读介质

    公开(公告)号：US06909878B2

    公开(公告)日：2005-06-21

    申请号：US10224749

    申请日：2002-08-20

    申请人： Amit Haller ,  Ziv Haparnas

    发明人： Amit Haller ,  Ziv Haparnas

    IPC分类号： H04H60/04 ,  H04M1/725 ,  H04Q7/32 ,  H04B5/00

    CPC分类号： H04M1/7253 ,  H04L67/04 ,  H04L67/06 ,  H04L67/303 ,  H04M2250/02

    摘要： A method, system, and computer readable medium allows a user to select an output signal for device/terminal in short distance wireless network. In embodiments of the present invention, the output signal is a ring tone, alarm, background image, vibration signal, font type, or portion of a motion picture. In embodiments of the present invention, a system comprises a first and second device, in a short distance wireless network, generating a first and second output signal. A cellular device generates a first and a second short-range radio signals responsive to a cellular signal from a cellular network. The cellular signal includes a first multimedia file for the first device and a second multimedia file for the second device. In an embodiment of the present invention, the first multimedia file and second multimedia file are thematically related. In an embodiment of the present invention, a processing device is coupled to the cellular network and stores the first and second multimedia files. In an embodiment of the present invention, a user selects a theme on a device or at a web site in order to change the output signals in the short distance wireless network. In an embodiment of the present invention, the output signals are changed periodically without user intervention. In still a further embodiment of the present invention, promoters or users pay a telecommunication network provider for conveniently and safely changing the output signals.

    摘要翻译： 方法，系统和计算机可读介质允许用户在短距离无线网络中选择设备/终端的输出信号。 在本发明的实施例中，输出信号是铃声，警报，背景图像，振动信号，字体类型或运动图像的一部分。 在本发明的实施例中，系统包括第一和第二设备，在短距离无线网络中，产生第一和第二输出信号。 蜂窝设备响应于来自蜂窝网络的蜂窝信号产生第一和第二短距离无线电信号。 蜂窝信号包括用于第一设备的第一多媒体文件和用于第二设备的第二多媒体文件。 在本发明的实施例中，第一多媒体文件和第二多媒体文件是主题相关的。 在本发明的实施例中，处理设备耦合到蜂窝网络并存储第一和第二多媒体文件。 在本发明的实施例中，用户在设备或网站上选择主题，以便改变短距离无线网络中的输出信号。 在本发明的实施例中，输出信号在没有用户干预的情况下周期性地改变。 在本发明的另一个实施例中，启动器或用户向电信网络提供商支付方便和安全地改变输出信号。