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US07007156B2 Multiple coprocessor architecture to process a plurality of subtasks in parallel 失效
多个协处理器架构并行处理多个子任务

Multiple coprocessor architecture to process a plurality of subtasks in parallel
摘要:
A programmed state processing machine architecture and method that provides improved efficiency for processing data manipulation tasks. In one embodiment, the processing machine comprises a control engine and a plurality coprocessors, a data memory, and an instruction memory. A sequence of instructions having a plurality of portions are issued by the instruction memory, wherein the control engine and each of the processors is caused to perform a specific task based on the portion of the instructions designated for that component. Accordingly, a data manipulation task can be divided into a plurality of subtasks that are processed in parallel by respective processing components in the architecture.
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