Invention Grant
- Patent Title: Multiple coprocessor architecture to process a plurality of subtasks in parallel
- Patent Title (中): 多个协处理器架构并行处理多个子任务
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Application No.: US09751943Application Date: 2000-12-28
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Publication No.: US07007156B2Publication Date: 2006-02-28
- Inventor: Gavin J. Stark , John Wishneusky
- Applicant: Gavin J. Stark , John Wishneusky
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakley, Sokoloff, Taylor & Zafman LLP
- Main IPC: G06F9/00
- IPC: G06F9/00

Abstract:
A programmed state processing machine architecture and method that provides improved efficiency for processing data manipulation tasks. In one embodiment, the processing machine comprises a control engine and a plurality coprocessors, a data memory, and an instruction memory. A sequence of instructions having a plurality of portions are issued by the instruction memory, wherein the control engine and each of the processors is caused to perform a specific task based on the portion of the instructions designated for that component. Accordingly, a data manipulation task can be divided into a plurality of subtasks that are processed in parallel by respective processing components in the architecture.
Public/Granted literature
- US20020087827A1 Architecture of psm-mpus and coprocessors Public/Granted day:2002-07-04
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