发明授权
- 专利标题: Chip scale package with open substrate
- 专利标题(中): 具有开放衬底的芯片级封装
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申请号: US10866561申请日: 2004-06-10
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公开(公告)号: US07008820B2公开(公告)日: 2006-03-07
- 发明人: Il Kwon Shim , Kwee Lan Tan , Jian Jun Li , Dario S. Filoteo, Jr.
- 申请人: Il Kwon Shim , Kwee Lan Tan , Jian Jun Li , Dario S. Filoteo, Jr.
- 申请人地址: SG Singapore
- 专利权人: ST Assembly Test Services Ltd.
- 当前专利权人: ST Assembly Test Services Ltd.
- 当前专利权人地址: SG Singapore
- 代理商 Mikio Ishimaru
- 主分类号: H01L21/44
- IPC分类号: H01L21/44 ; H01L21/48 ; H01L21/50
摘要:
A method for manufacturing an integrated circuit package comprises forming a substrate by forming a core layer with a through opening and vias. A first conductive layer is formed on the core layer covering the through opening and a second conductive layer is formed on the core layer opposite the first conductive layer in the through opening and in the vias contacting the first conductive layer. An integrated circuit die is bonded to the second conductive layer and in the through opening. Connections are formed between the integrated circuit die and the second conductive layer, and the integrated circuit die and the connections are encapsulated.
公开/授权文献
- US20050277227A1 CHIP SCALE PACKAGE WITH OPEN SUBSTRATE 公开/授权日:2005-12-15
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