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公开(公告)号：US08030783B2
公开(公告)日：2011-10-04
申请号：US12582587
申请日：2009-10-20
申请人： Il Kwon Shim , Kwee Lan Tan , Jian Jun Li , Dario S. Filoteo, Jr.
发明人： Il Kwon Shim , Kwee Lan Tan , Jian Jun Li , Dario S. Filoteo, Jr.
IPC分类号： H01L29/40
CPC分类号： H01L25/0657 , H01L21/4857 , H01L23/13 , H01L23/49816 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48237 , H01L2224/73265 , H01L2225/0651 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06586 , H01L2225/1058 , H01L2924/00014 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , Y10S438/928 , H01L2924/00012 , H01L2924/01031 , H01L2924/00 , H01L2924/3512 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of manufacturing an integrated circuit package includes: forming a substrate that includes: forming a core layer, forming vias in the core layer, and forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer.
摘要翻译： 制造集成电路封装的方法包括：形成衬底，其包括：形成芯层，在芯层中形成通孔，以及在芯层上形成具有预定厚度的导电层，并且在 过孔 以及在集成电路管芯和导电层之间形成连接。
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2.发明申请INTEGRATED CIRCUIT PACKAGE WITH OPEN SUBSTRATE AND METHOD OF MANUFACTURING THEREOF 有权具有开放基板的集成电路封装及其制造方法公开(公告)号：US20120018886A1
公开(公告)日：2012-01-26
申请号：US13247890
申请日：2011-09-28
申请人： Il Kwon Shim , Kwee Lan Tan , Jian Jun Li , Dario S. Filoteo, JR.
发明人： Il Kwon Shim , Kwee Lan Tan , Jian Jun Li , Dario S. Filoteo, JR.
IPC分类号： H01L23/498 , H01L21/56
CPC分类号： H01L25/0657 , H01L21/4857 , H01L23/13 , H01L23/49816 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48237 , H01L2224/73265 , H01L2225/0651 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06586 , H01L2225/1058 , H01L2924/00014 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , Y10S438/928 , H01L2924/00012 , H01L2924/01031 , H01L2924/00 , H01L2924/3512 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of manufacturing an integrated circuit package includes: forming a substrate including: forming a core layer, and forming vias in the core layer; forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer.
摘要翻译： 制造集成电路封装的方法包括：形成衬底，包括：形成芯层，并在芯层中形成通孔; 在芯层上形成具有预定厚度的导电层，并且在通孔中基本上具有预定厚度的两倍; 以及在集成电路管芯和导电层之间形成连接。
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公开(公告)号：US20100038771A1
公开(公告)日：2010-02-18
申请号：US12582587
申请日：2009-10-20
申请人： Il Kwon Shim , Kwee Lan Tan , Jian Jun Li , Dario S. Filoteo, JR.
发明人： Il Kwon Shim , Kwee Lan Tan , Jian Jun Li , Dario S. Filoteo, JR.
IPC分类号： H01L23/498 , H01L21/56
CPC分类号： H01L25/0657 , H01L21/4857 , H01L23/13 , H01L23/49816 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48237 , H01L2224/73265 , H01L2225/0651 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06586 , H01L2225/1058 , H01L2924/00014 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , Y10S438/928 , H01L2924/00012 , H01L2924/01031 , H01L2924/00 , H01L2924/3512 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of manufacturing an integrated circuit package includes: forming a substrate that includes: forming a core layer, forming vias in the core layer, and forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer.
摘要翻译： 制造集成电路封装的方法包括：形成衬底，其包括：形成芯层，在芯层中形成通孔，以及在芯层上形成具有预定厚度的导电层，并且在 过孔 以及在集成电路管芯和导电层之间形成连接。
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公开(公告)号：US07626277B2
公开(公告)日：2009-12-01
申请号：US11164329
申请日：2005-11-18
申请人： Il Kwon Shim , Kwee Lan Tan , Jian Jun Li , Dario S. Filoteo, Jr.
发明人： Il Kwon Shim , Kwee Lan Tan , Jian Jun Li , Dario S. Filoteo, Jr.
CPC分类号： H01L25/0657 , H01L21/4857 , H01L23/13 , H01L23/49816 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48237 , H01L2224/73265 , H01L2225/0651 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06586 , H01L2225/1058 , H01L2924/00014 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , Y10S438/928 , H01L2924/00012 , H01L2924/01031 , H01L2924/00 , H01L2924/3512 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An integrated circuit package comprises a substrate including a core layer with a through opening and vias. A first conductive layer is on the core layer covering the through opening and a second conductive layer is on the core layer opposite the first conductive layer in the through opening and in the vias contacting the first conductive layer. An integrated circuit die is bonded to the second conductive layer and in the through opening. Connections are between the integrated circuit die and the second conductive layer, and the integrated circuit die and the connections are encapsulated.
摘要翻译： 集成电路封装包括具有通孔和通孔的芯层的衬底。 第一导电层位于覆盖通孔的芯层上，第二导电层位于与贯通孔中的第一导电层相对的芯层和接触第一导电层的通孔中。 集成电路管芯结合到第二导电层和通孔中。 连接在集成电路管芯和第二导电层之间，并且集成电路管芯和连接被封装。
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5.发明授权Integrated circuit package with open substrate and method of manufacturing thereof 有权具有开放衬底的集成电路封装及其制造方法公开(公告)号：US09034693B2
公开(公告)日：2015-05-19
申请号：US13247890
申请日：2011-09-28
申请人： Il Kwon Shim , Kwee Lan Tan , Jian Jun Li , Dario S. Filoteo, Jr.
发明人： Il Kwon Shim , Kwee Lan Tan , Jian Jun Li , Dario S. Filoteo, Jr.
IPC分类号： H01L21/00 , H01L25/065 , H01L21/48 , H01L23/13 , H01L23/498 , H01L25/10 , H01L23/00
CPC分类号： H01L25/0657 , H01L21/4857 , H01L23/13 , H01L23/49816 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48237 , H01L2224/73265 , H01L2225/0651 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06586 , H01L2225/1058 , H01L2924/00014 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , Y10S438/928 , H01L2924/00012 , H01L2924/01031 , H01L2924/00 , H01L2924/3512 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of manufacturing an integrated circuit package includes: forming a substrate including: forming a core layer, and forming vias in the core layer; forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer.
摘要翻译： 制造集成电路封装的方法包括：形成衬底，包括：形成芯层，并在芯层中形成通孔; 在芯层上形成具有预定厚度的导电层，并且在通孔中基本上具有预定厚度的两倍; 以及在集成电路管芯和导电层之间形成连接。
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公开(公告)号：US20060055009A1
公开(公告)日：2006-03-16
申请号：US11164329
申请日：2005-11-18
申请人： Il Kwon Shim , Kwee Lan Tan , Jian Jun Li , Dario Filoteo
发明人： Il Kwon Shim , Kwee Lan Tan , Jian Jun Li , Dario Filoteo
IPC分类号： H01L23/495
CPC分类号： H01L25/0657 , H01L21/4857 , H01L23/13 , H01L23/49816 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48237 , H01L2224/73265 , H01L2225/0651 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06586 , H01L2225/1058 , H01L2924/00014 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , Y10S438/928 , H01L2924/00012 , H01L2924/01031 , H01L2924/00 , H01L2924/3512 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An integrated circuit package comprises a substrate including a core layer with a through opening and vias. A first conductive layer is on the core layer covering the through opening and a second conductive layer is on the core layer opposite the first conductive layer in the through opening and in the vias contacting the first conductive layer. An integrated circuit die is bonded to the second conductive layer and in the through opening. Connections are between the integrated circuit die and the second conductive layer, and the integrated circuit die and the connections are encapsulated.
摘要翻译： 集成电路封装包括具有通孔和通孔的芯层的衬底。 第一导电层位于覆盖通孔的芯层上，第二导电层位于与贯通孔中的第一导电层相对的芯层和接触第一导电层的通孔中。 集成电路管芯结合到第二导电层和通孔中。 连接在集成电路管芯和第二导电层之间，并且集成电路管芯和连接被封装。
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公开(公告)号：US07008820B2
公开(公告)日：2006-03-07
申请号：US10866561
申请日：2004-06-10
申请人： Il Kwon Shim , Kwee Lan Tan , Jian Jun Li , Dario S. Filoteo, Jr.
发明人： Il Kwon Shim , Kwee Lan Tan , Jian Jun Li , Dario S. Filoteo, Jr.
CPC分类号： H01L25/0657 , H01L21/4857 , H01L23/13 , H01L23/49816 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48237 , H01L2224/73265 , H01L2225/0651 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06586 , H01L2225/1058 , H01L2924/00014 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , Y10S438/928 , H01L2924/00012 , H01L2924/01031 , H01L2924/00 , H01L2924/3512 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method for manufacturing an integrated circuit package comprises forming a substrate by forming a core layer with a through opening and vias. A first conductive layer is formed on the core layer covering the through opening and a second conductive layer is formed on the core layer opposite the first conductive layer in the through opening and in the vias contacting the first conductive layer. An integrated circuit die is bonded to the second conductive layer and in the through opening. Connections are formed between the integrated circuit die and the second conductive layer, and the integrated circuit die and the connections are encapsulated.
摘要翻译： 一种用于制造集成电路封装的方法包括通过形成具有通孔和通孔的芯层来形成衬底。 在覆盖通孔的芯层上形成第一导电层，在与第一导电层接触的通路中的与第一导电层相对的芯层上形成第二导电层。 集成电路管芯结合到第二导电层和通孔中。 在集成电路管芯和第二导电层之间形成连接，并且封装集成电路管芯和连接。
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