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US07010675B2 Fetch branch architecture for reducing branch penalty without branch prediction 有权
获取分支结构，以减少分支惩罚，无需分支预测

  • 专利标题： Fetch branch architecture for reducing branch penalty without branch prediction
  • 专利标题（中）： 获取分支结构，以减少分支惩罚，无需分支预测
  • 申请号： US09917290
    申请日： 2001-07-27
  • 公开(公告)号： US07010675B2
    公开(公告)日： 2006-03-07
  • 发明人: Faraydon O. Karim , Ramesh Chandra
  • 申请人： Faraydon O. Karim , Ramesh Chandra
  • 申请人地址： US TX Carrollton
  • 专利权人： STMicroelectronics, Inc.
  • 当前专利权人： STMicroelectronics, Inc.
  • 当前专利权人地址： US TX Carrollton
  • 代理商 Lisa K. Jorgenson; William A. Munck
  • 主分类号： G06F9/30
  • IPC分类号： G06F9/30
Fetch branch architecture for reducing branch penalty without branch prediction
摘要：
In lieu of branch prediction, a merged fetch-branch unit operates in parallel with the decode unit within a processor. Upon detection of a branch instruction within a group of one or more fetched instructions, any instructions preceding the branch are marked regular instructions, the branch instruction is marked as such, and any instructions following branch are marked sequential instructions. Within two cycles, sequential instructions following the last fetched instruction are retrieved and marked, target instructions beginning at the branch target address are retrieved and marked, and the branch is resolved. Either the sequential or target instructions are then dropped depending on the branch resolution, incurring a fixed, 1 cycle branch penalty.
摘要（中）：

代替分支预测，合并的分支单元与处理器内的解码单元并行操作。 在检测到一个或多个获取的指令的组内的分支指令时，分支之前的任何指令被标记为常规指令，分支指令被标记为这样，并且分支之后的任何指令被标记为顺序指令。 在两个周期内，检索并标记最后取出的指令之后的顺序指令，检索并标记从分支目标地址开始的目标指令，并解析分支。 然后根据分支分辨率，顺序或目标指令被丢弃，产生固定的1个循环分支罚分。

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