Invention Grant
- Patent Title: Localized masking for semiconductor structure development
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Application No.: US10453229Application Date: 2003-06-03
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Publication No.: US07015529B2Publication Date: 2006-03-21
- Inventor: Donald L. Yates , Garry A. Mercaldi
- Applicant: Donald L. Yates , Garry A. Mercaldi
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman, Lundberg, Woessner & Kluth, P.A.
- Main IPC: H01L29/78
- IPC: H01L29/78

Abstract:
Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface layers. The localized masking is accomplished through differential exposure of a resist layer to electromagnetic or thermal energy. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.
Public/Granted literature
- US20030205749A1 Localized masking for semiconductor structure development Public/Granted day:2003-11-06
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