- 专利标题： Transistor with strain-inducing structure in channel
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申请号： US10714139申请日： 2003-11-14
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公开(公告)号： US07019326B2公开(公告)日： 2006-03-28
- 发明人: Stephen M. Cea , Ravindra Soman , Ramune Nagisetty , Sunit Tyagi , Sanjay Natarajan
- 申请人： Stephen M. Cea , Ravindra Soman , Ramune Nagisetty , Sunit Tyagi , Sanjay Natarajan
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Blakely, Sokoloff, Taylor & Zafman LLP
- 主分类号： H01L29/06
- IPC分类号： H01L29/06
摘要：
Various methods for forming a layer of strained silicon in a channel region of a device and devices constructed according to the disclosed methods. In one embodiment, a strain-inducing layer is formed, a relaxed layer is formed on the strain-inducing layer, a portion of the strain-inducing layer is removed, which allows the strain-inducing layer to relax and strain the relaxed layer.
公开/授权文献
- US20050106792A1 Transistor with strain-inducing structure in channel 公开/授权日：2005-05-19
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