发明授权
US07023372B1 Method and apparatus for segmented, switched analog/digital converter 有权
用于分段,开关模拟/数字转换器的方法和装置

Method and apparatus for segmented, switched analog/digital converter
摘要:
A switched-capacitor circuit for use in analog-to-digital conversion samples an input signal with respect to a reference voltage such that it significantly reduces a DAC settling time interval during each bit trial. In one exemplary embodiment, the switched-capacitor circuit having first and second groups of capacitor banks is coupled to a first input of a comparator and to a control circuit which provides control signals such that during a switching sequence, an equal value of capacitance is selected from each of the first and second groups of capacitor banks to reduce the DAC settling time interval, thereby improving the conversion rate.
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