公开(公告)号：US07023372B1

公开(公告)日：2006-04-04

申请号：US11054064

申请日：2005-02-09

申请人： Ramesh Singh ,  Eamonn Byrne ,  Asif Ahmad ,  Srikanth Nittala ,  Shubha Govindachar

发明人： Ramesh Singh ,  Eamonn Byrne ,  Asif Ahmad ,  Srikanth Nittala ,  Shubha Govindachar

IPC分类号： H03M1/12

CPC分类号： H03M1/0682 ,  H03M1/468 ,  H03M1/806

摘要： A switched-capacitor circuit for use in analog-to-digital conversion samples an input signal with respect to a reference voltage such that it significantly reduces a DAC settling time interval during each bit trial. In one exemplary embodiment, the switched-capacitor circuit having first and second groups of capacitor banks is coupled to a first input of a comparator and to a control circuit which provides control signals such that during a switching sequence, an equal value of capacitance is selected from each of the first and second groups of capacitor banks to reduce the DAC settling time interval, thereby improving the conversion rate.

摘要翻译： 用于模数转换的开关电容电路针对参考电压对输入信号进行采样，从而在每个位试验期间显着降低DAC稳定时间间隔。 在一个示例性实施例中，具有第一组和第二组电容器组的开关电容器电路耦合到比较器的第一输入端，并提供给控制电路，该控制电路提供控制信号，使得在切换序列期间，选择相等的电容值 从第一组和第二组电容器组中的每一个减少DAC建立时间间隔，从而提高转换速率。