Invention Grant
- Patent Title: Parasitic capacitance-preventing dummy solder bump structure and method of making the same
- Patent Title (中): 寄生电容防止假焊料凸块结构及其制造方法
-
Application No.: US10709940Application Date: 2004-06-08
-
Publication No.: US07026234B2Publication Date: 2006-04-11
- Inventor: Jui-Meng Jao , Shing-Ren Sheu , Kuo-Ming Chen , Hung-Min Liu , Kun-Chih Wang
- Applicant: Jui-Meng Jao , Shing-Ren Sheu , Kuo-Ming Chen , Hung-Min Liu , Kun-Chih Wang
- Applicant Address: TW Hsin-Chu
- Assignee: United Microelectronics Corp.
- Current Assignee: United Microelectronics Corp.
- Current Assignee Address: TW Hsin-Chu
- Agent Winston Hsu
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L29/40
Abstract:
A parasitic capacitance-preventing dummy solder bump structure on a substrate has at least one conductive layer formed on the substrate, a dielectric layer employed to cover the conductive layer, an under bump metallurgy layer (UBM layer) formed on the dielectric layer, and a solder bump formed on the UBM layer.
Public/Granted literature
- US20040266160A1 PARASITIC CAPACITANCE-PREVENTING DUMMY SOLDER BUMP STRUCTURE AND METHOD OF MAKING THE SAME Public/Granted day:2004-12-30
Information query
IPC分类:
