公开(公告)号：US08605235B2

公开(公告)日：2013-12-10

申请号：US12779915

申请日：2010-05-13

申请人： Chih-Wei Lin ,  Min-Cheng Wang ,  Yung-Cheng Chen ,  Hung-Min Liu

发明人： Chih-Wei Lin ,  Min-Cheng Wang ,  Yung-Cheng Chen ,  Hung-Min Liu

IPC分类号： G02F1/1335

CPC分类号： G01B11/24 ,  G01B5/061 ,  G01B11/00 ,  G01B11/02 ,  G01B11/0608 ,  G01B11/08 ,  G01B17/02 ,  G02F1/133512 ,  G02F1/13394 ,  G03F7/70625

摘要： A display device and a method of measuring a surface structure of the same are provided. The display device includes first and second substrates, first and second patterned light-shielding layers, and first and second pixel units. The first patterned light-shielding layer disposed on a surface of the first substrate includes first openings. The second patterned light-shielding layer disposed on the surface of the first substrate in the first patterned light-shielding layer includes second openings. The first pixel unit includes first and second protrusions. The first protrusion correspondingly covers the first openings and a portion of the first patterned light-shielding layer. The second protrusion is disposed in the first and second patterned light-shielding layers. The second pixel unit includes a third protrusion correspondingly covering the second openings and a portion of the second patterned light-shielding layer, wherein sizes of the second openings are smaller than sizes of the first openings.

摘要翻译： 提供显示装置和测量其表面结构的方法。 显示装置包括第一和第二基板，第一和第二图案化遮光层以及第一和第二像素单元。 设置在第一基板的表面上的第一图案化遮光层包括第一开口。 设置在第一图案化遮光层中的第一基板的表面上的第二图案遮光层包括第二开口。 第一像素单元包括第一和第二突起。 第一突起相应地覆盖第一开口和第一图案化遮光层的一部分。 第二突起设置在第一和第二图案化的遮光层中。 第二像素单元包括对应地覆盖第二开口的第三突起和第二图案化遮光层的一部分，其中第二开口的尺寸小于第一开口的尺寸。

公开(公告)号：US20050164428A1

公开(公告)日：2005-07-28

申请号：US10907702

申请日：2005-04-12

申请人： Hung-Min Liu ,  Kow-Bao Chen

发明人： Hung-Min Liu ,  Kow-Bao Chen

IPC分类号： G01R1/067 ,  G01R31/28 ,  H01L23/485 ,  H01L21/44 ,  H01L21/48

CPC分类号： G01R31/2886 ,  G01R1/06738 ,  H01L24/10 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  Y10T436/17 ,  H01L2924/00014

摘要： The present invention provides a novel probe tip suited for flip-chip packaging process. The probe tip comprises a needle body; and a stop cylinder having a recess for fittingly accommodating the needle body therein, the needle body being electrically connected to the stop cylinder via a resilient conductive material. The stop cylinder has an annual flat bottom surrounding the needle body for pressing a protruding probe mark on a metal pad scratched by the needle body.

摘要翻译： 本发明提供了适用于倒装芯片封装工艺的新型探针尖端。 探针尖端包括针体; 以及具有用于将针体适当地容纳在其中的凹部的止动圆筒，所述针体通过弹性导电材料电连接到止动圆筒。 止动圆筒具有围绕针体的年度平底，用于按压由针体划伤的金属垫上的突出探针标记。

公开(公告)号：US20050032229A1

公开(公告)日：2005-02-10

申请号：US10604611

申请日：2003-08-05

申请人： Hung-Min Liu ,  Kow-Bao Chen

发明人： Hung-Min Liu ,  Kow-Bao Chen

IPC分类号： G01R1/067 ,  G01R31/28 ,  H01L23/485 ,  H01L21/44

CPC分类号： G01R31/2886 ,  G01R1/06738 ,  H01L24/10 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  Y10T436/17 ,  H01L2924/00014

摘要： The present invention provides a novel probe tip suited for flip-chip packaging process. The probe tip comprises a needle body; and a stop cylinder having a recess for fittingly accommodating the needle body therein, the needle body being electrically connected to the stop cylinder via a resilient conductive material. The stop cylinder has an annual flat bottom surrounding the needle body for pressing a protruding probe mark on a metal pad scratched by the needle body.

摘要翻译： 本发明提供了适用于倒装芯片封装工艺的新型探针尖端。 探针尖端包括针体; 以及具有用于将针体适当地容纳在其中的凹部的止动圆筒，所述针体通过弹性导电材料电连接到止动圆筒。 止动圆筒具有围绕针体的年度平底，用于按压由针体划伤的金属垫上的突出探针标记。

公开(公告)号：US20050002167A1

公开(公告)日：2005-01-06

申请号：US10610638

申请日：2003-07-02

申请人： John Hsuan ,  Kuo-Ming Chen ,  Kow-Bao Chen ,  Hung-Min Liu ,  Kai-Kuang Ho

发明人： John Hsuan ,  Kuo-Ming Chen ,  Kow-Bao Chen ,  Hung-Min Liu ,  Kai-Kuang Ho

IPC分类号： H01L23/498 ,  H01L25/16 ,  H05K1/02 ,  H05K3/34 ,  H05K7/06

CPC分类号： H01L25/165 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/30107 ,  H05K1/023 ,  H05K3/3436 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： An improved microelectronic package is disclosed. The microelectronic package includes a packaging substrate having an upper surface and an underside. At least one chip is mounted on the upper surface of the packaging substrate. A plurality of ball grid array (BGA) solder balls are mounted at the underside of the packaging substrate. At least one RC passive component is disposed underneath the chip. The chip may be mounted on predetermined position on the upper surface of the packaging substrate with solder bumps by using Flip-Chip (FC) assembly method. According to one aspect of the present invention, the RC passive component is disposed between the BGA solder balls. According to one aspect of the present invention, the RC passive component is an adjustable resist having a plurality of bumps formed thereon, and wherein two metal trace lines, which correspond to two bumps of the plural bumps, are provided on the underside of the packaging substrate. The distance between the two metal trace lines determines the resistance value of the adjustable resist.

摘要翻译： 公开了一种改进的微电子封装。 微电子封装包括具有上表面和下表面的封装衬底。 至少一个芯片安装在封装基板的上表面上。 多个球栅阵列（BGA）焊球安装在封装基板的下侧。 至少一个RC无源元件设置在芯片下方。 通过使用倒装芯片（FC）组装方法，芯片可以通过焊料凸块安装在包装衬底的上表面上的预定位置上。 根据本发明的一个方面，RC无源部件设置在BGA焊球之间。 根据本发明的一个方面，RC无源元件是一种可调节的抗蚀剂，其上形成有多个凸点，并且其中两个对应于多个凸块的两个凸块的金属迹线设置在封装的下侧 基质。 两条金属轨迹线之间的距离决定了可调节抗蚀剂的电阻值。

公开(公告)号：US20110128481A1

公开(公告)日：2011-06-02

申请号：US12779915

申请日：2010-05-13

申请人： Chih-Wei Lin ,  Min-Cheng Wang ,  Yung-Cheng Chen ,  Hung-Min Liu

发明人： Chih-Wei Lin ,  Min-Cheng Wang ,  Yung-Cheng Chen ,  Hung-Min Liu

IPC分类号： G02F1/1335 ,  G02F1/167 ,  G01B11/00

CPC分类号： G01B11/24 ,  G01B5/061 ,  G01B11/00 ,  G01B11/02 ,  G01B11/0608 ,  G01B11/08 ,  G01B17/02 ,  G02F1/133512 ,  G02F1/13394 ,  G03F7/70625

摘要： A display device and a method of measuring a surface structure of the same are provided. The display device includes first and second substrates, first and second patterned light-shielding layers, and first and second pixel units. The first patterned light-shielding layer disposed on a surface of the first substrate includes first openings. The second patterned light-shielding layer disposed on the surface of the first substrate in the first patterned light-shielding layer includes second openings. The first pixel unit includes first and second protrusions. The first protrusion correspondingly covers the first openings and a portion of the first patterned light-shielding layer. The second protrusion is disposed in the first and second patterned light-shielding layers. The second pixel unit includes a third protrusion correspondingly covering the second openings and a portion of the second patterned light-shielding layer, wherein sizes of the second openings are smaller than sizes of the first openings.

摘要翻译： 提供显示装置和测量其表面结构的方法。 显示装置包括第一和第二基板，第一和第二图案化遮光层以及第一和第二像素单元。 设置在第一基板的表面上的第一图案化遮光层包括第一开口。 设置在第一图案化遮光层中的第一基板的表面上的第二图案遮光层包括第二开口。 第一像素单元包括第一和第二突起。 第一突起相应地覆盖第一开口和第一图案化遮光层的一部分。 第二突起设置在第一和第二图案化的遮光层中。 第二像素单元包括对应地覆盖第二开口的第三突起和第二图案化遮光层的一部分，其中第二开口的尺寸小于第一开口的尺寸。

公开(公告)号：US07026234B2

公开(公告)日：2006-04-11

申请号：US10709940

申请日：2004-06-08

申请人： Jui-Meng Jao ,  Shing-Ren Sheu ,  Kuo-Ming Chen ,  Hung-Min Liu ,  Kun-Chih Wang

发明人： Jui-Meng Jao ,  Shing-Ren Sheu ,  Kuo-Ming Chen ,  Hung-Min Liu ,  Kun-Chih Wang

IPC分类号： H01L21/44 ,  H01L29/40

CPC分类号： H01L24/13 ,  H01L23/5222 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/0508 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166

摘要： A parasitic capacitance-preventing dummy solder bump structure on a substrate has at least one conductive layer formed on the substrate, a dielectric layer employed to cover the conductive layer, an under bump metallurgy layer (UBM layer) formed on the dielectric layer, and a solder bump formed on the UBM layer.

摘要翻译： 衬底上的寄生电容防止虚拟焊料凸块结构具有至少一个形成在衬底上的导电层，用于覆盖导电层的电介质层，形成在电介质层上的凸块下金属层（UBM层）和 焊料凸块形成在UBM层上。

公开(公告)号：US07008818B2

公开(公告)日：2006-03-07

申请号：US10907702

申请日：2005-04-12

申请人： Hung-Min Liu ,  Kow-Bao Chen

发明人： Hung-Min Liu ,  Kow-Bao Chen

IPC分类号： H01L21/50

CPC分类号： G01R31/2886 ,  G01R1/06738 ,  H01L24/10 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  Y10T436/17 ,  H01L2924/00014

摘要： The present invention provides a novel probe tip suited for flip-chip packaging process. The probe tip comprises a needle body; and a stop cylinder having a recess for fittingly accommodating the needle body therein, the needle body being electrically connected to the stop cylinder via a resilient conductive material. The stop cylinder has an annual flat bottom surrounding the needle body for pressing a protruding probe mark on a metal pad scratched by the needle body.

摘要翻译： 本发明提供了适用于倒装芯片封装工艺的新型探针尖端。 探针尖端包括针体; 以及具有用于将针体适当地容纳在其中的凹部的止动圆筒，所述针体通过弹性导电材料电连接到止动圆筒。 止动圆筒具有围绕针体的年度平底，用于按压由针体划伤的金属垫上的突出探针标记。

公开(公告)号：US07268440B2

公开(公告)日：2007-09-11

申请号：US10905534

申请日：2005-01-09

申请人： Zong-Huei Lin ,  Hung-Min Liu ,  Jui-Meng Jao ,  Wen-Tung Chang ,  Kuo-Ming Chen ,  Kai-Kuang Ho

发明人： Zong-Huei Lin ,  Hung-Min Liu ,  Jui-Meng Jao ,  Wen-Tung Chang ,  Kuo-Ming Chen ,  Kai-Kuang Ho

IPC分类号： H01L23/544

CPC分类号： H01L22/34 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor wafer includes a plurality of active circuit die areas, each of which being bordered by a dicing line region through which the plurality of active circuit die areas are separated from each other by mechanical wafer dicing. Each of the plurality of active circuit die areas has four sides. An overcoat covers both the active circuit die areas and the dicing line region. An inter-layer dielectric layer is disposed underneath the overcoat. A reinforcement structure includes a plurality of holes formed within the dicing line region. The plurality of holes are formed by etching through the overcoat into the inter-layer dielectric layer and are disposed along the four sides of each active circuit die area. A die seal ring is disposed in between the active circuit chip area and the reinforcement structure.

摘要翻译： 半导体晶片包括多个有源电路管芯区域，每个有源电路管芯区域由切割线区域界定，多个有源电路管芯区域通过该切割线区域通过机械晶片切割彼此分离。 多个有源电路管芯区域中的每一个具有四个侧面。 覆盖层覆盖有源电路裸片区域和切割线区域。 层间介电层设置在外涂层的下方。 加强结构包括形成在切割线区域内的多个孔。 通过将外涂层蚀刻到层间电介质层中并沿着每个有源电路管芯区域的四个侧面设置多个孔。 模具密封环设置在有源电路芯片区域和加强结构之间。

公开(公告)号：US06881654B2

公开(公告)日：2005-04-19

申请号：US10065568

申请日：2002-10-31

申请人： Kuo-Ming Chen ,  Hung-Min Liu

发明人： Kuo-Ming Chen ,  Hung-Min Liu

IPC分类号： H01L21/20 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L23/525 ,  H01L23/544

CPC分类号： H01L21/76894 ,  H01L23/5256 ,  H01L23/544 ,  H01L24/02 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/00

摘要： A solder bump structure and laser repair process for memory device include forming a first dielectric layer on a bump pad of a semiconductor wafer. After that, the first dielectric layer is etched to form a contact hole and to expose portions of the bump pad. A second dielectric layer is then formed on a surface of the semiconductor wafer outside of the contact hole. An under bump metallurgy (UBM) process is performed to form a metal layer on a surface of the contact hole, and a solder bump is formed on the metal layer. Finally, the laser repair process for memory device is completed.

摘要翻译： 用于存储器件的焊料凸块结构和激光修复工艺包括在半导体晶片的凸块焊盘上形成第一电介质层。 之后，蚀刻第一电介质层以形成接触孔并暴露凸块焊盘的部分。 然后在接触孔外部的半导体晶片的表面上形成第二电介质层。 执行凸块下金属（UBM）工艺以在接触孔的表面上形成金属层，并且在金属层上形成焊料凸块。 最后，完成了存储器件的激光修复过程。

公开(公告)号：US20060278957A1

公开(公告)日：2006-12-14

申请号：US11160106

申请日：2005-06-09

申请人： Zong-Huei Lin ,  Hung-Min Liu ,  Jui-Meng Jao ,  Wen-Tung Chang ,  Kuo-Ming Chen ,  Kai-Kuang Ho

发明人： Zong-Huei Lin ,  Hung-Min Liu ,  Jui-Meng Jao ,  Wen-Tung Chang ,  Kuo-Ming Chen ,  Kai-Kuang Ho

IPC分类号： H01L23/544

CPC分类号： H01L21/78

摘要： A semiconductor wafer includes a plurality of active circuit die areas, each of which being bordered by a dicing line region through which the plurality of active circuit die areas are separated from each other, wherein each of the plurality of active circuit die areas has substantially four corners. An overcoat is deposited to cover both the active circuit die areas and the dicing line region. A first trench is formed by etching through the overcoat and disposed merely around the four corners of each active circuit die area. A reinforcing second trench is etched into the overcoat and is disposed in proximity to the first trench. A die seal ring is disposed in between the active circuit chip area and the first trench.

摘要翻译： 半导体晶片包括多个有源电路管芯区域，每个有源电路管芯区域由多个有源电路管芯区域彼此分离的切割线区域界定，其中多个有源电路管芯区域中的每一个具有基本上四个 角落 沉积外涂层以覆盖有源电路裸片区域和切割线区域。 通过蚀刻穿过外涂层并且仅设置在每个有源电路管芯区域的四个角落周围形成第一沟槽。 加强第二沟槽被蚀刻到外涂层中并且设置在第一沟槽附近。 模具密封环设置在有源电路芯片区域和第一沟槽之间。