Invention Grant
- Patent Title: Low profile chip scale stacking system and method
- Patent Title (中): 薄型芯片级堆叠系统及方法
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Application No.: US10631886Application Date: 2003-07-11
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Publication No.: US07026708B2Publication Date: 2006-04-11
- Inventor: James W. Cady , Julian Partridge , James Douglas Wehrly, Jr. , James Wilder , David L. Roper , Jeff Buchle
- Applicant: James W. Cady , Julian Partridge , James Douglas Wehrly, Jr. , James Wilder , David L. Roper , Jeff Buchle
- Applicant Address: US TX Austin
- Assignee: Staktek Group L.P.
- Current Assignee: Staktek Group L.P.
- Current Assignee Address: US TX Austin
- Agency: Andrews Kurth LLP
- Agent J. Scott Denko
- Main IPC: H01L23/488
- IPC: H01L23/488 ; H05K1/14
Abstract:
The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile contacts are created by any of a variety of methods and materials. A consolidated low profile contact structure and technique is provided for use in alternative embodiments of the present invention. Multiple numbers of CSPs may be stacked in accordance with the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry that exhibit one or two or more conductive layers.
Public/Granted literature
- US20040052060A1 Low profile chip scale stacking system and method Public/Granted day:2004-03-18
Information query
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