Invention Grant
- Patent Title: Systems and methods for operating logic circuits
- Patent Title (中): 用于操作逻辑电路的系统和方法
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Application No.: US10764179Application Date: 2004-01-23
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Publication No.: US07030658B2Publication Date: 2006-04-18
- Inventor: Hiroaki Murakami , Osamu Takahashi , Jieming Qi
- Applicant: Hiroaki Murakami , Osamu Takahashi , Jieming Qi
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: DLA Piper Rudnick Gray Cary US LLP
- Main IPC: H03K19/20
- IPC: H03K19/20

Abstract:
Systems and methods for reducing the power consumption of some combinations of logic gates by reducing the number of unnecessary transitions that are made by logic gates that do not affect the output of the logic. In one embodiment, a modified exclusive-OR (XOR) gate is coupled to a modified multiplexer. The XOR gate has two inputs, Ain and Bin, and an output, XORout, which is provided as an input to the multiplexer. Another input to the multiplexer is Cin. A select signal is input to the multiplexer to select either Cin or XORout to be provided at the output of the multiplexer. If XORout is selected, the XOR gate operates in a first mode in which it functions as a normal XOR gate. If Cin is selected, the XOR gate operates in a second mode in which the XOR gate uses less power than when the XOR gate operates normally.
Public/Granted literature
- US20050162186A1 Systems and methods for operating logic circuits Public/Granted day:2005-07-28
Information query
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