公开(公告)号：US20050162186A1

公开(公告)日：2005-07-28

申请号：US10764179

申请日：2004-01-23

申请人： Hiroaki Murakami ,  Osamu Takahashi ,  Jieming Qi

发明人： Hiroaki Murakami ,  Osamu Takahashi ,  Jieming Qi

IPC分类号： G05B19/05 ,  H03K19/00 ,  H03K19/173 ,  H03K19/20

CPC分类号： H03K19/1737 ,  H03K19/0016

摘要： Systems and methods for reducing the power consumption of some combinations of logic gates by reducing the number of unnecessary transitions that are made by logic gates that do not affect the output of the logic. In one embodiment, a modified exclusive-OR (XOR) gate is coupled to a modified multiplexer. The XOR gate has two inputs, Ain, and Bin, and an output, XORout, which is provided as an input to the multiplexer. Another input to the multiplexer is Cin. A select signal is input to the multiplexer to select either Cin or XORout to be provided at the output of the multiplexer. If XORout is selected, the XOR gate operates in a first mode in which it functions as a normal XOR gate. If Cin is selected, the XOR gate operates in a second mode in which the XOR gate uses less power than when the XOR gate operates normally.

摘要翻译： 通过减少不影响逻辑输出的逻辑门进行的不必要的转换次数来减少逻辑门的某些组合的功耗的系统和方法。 在一个实施例中，修改的异或（XOR）门耦合到修改的多路复用器。 异或门具有两个输入：中的A _{和中的B ，输出XOR 输出，作为输入 复用器。 复用器的另一个输入是中的C 。 选择信号被输入到多路复用器以选择要在多路复用器的输出处提供的或XOR 输出中的C 。 如果选择XOR ，则异或门以第一模式工作，其中它用作正常的异或门。 如果选择了中的C ，则异或门以第二模式工作，其中XOR门比XOR门正常工作时使用的功率更小。}

公开(公告)号：US07030658B2

公开(公告)日：2006-04-18

申请号：US10764179

申请日：2004-01-23

申请人： Hiroaki Murakami ,  Osamu Takahashi ,  Jieming Qi

发明人： Hiroaki Murakami ,  Osamu Takahashi ,  Jieming Qi

IPC分类号： H03K19/20

CPC分类号： H03K19/1737 ,  H03K19/0016

摘要： Systems and methods for reducing the power consumption of some combinations of logic gates by reducing the number of unnecessary transitions that are made by logic gates that do not affect the output of the logic. In one embodiment, a modified exclusive-OR (XOR) gate is coupled to a modified multiplexer. The XOR gate has two inputs, Ain and Bin, and an output, XORout, which is provided as an input to the multiplexer. Another input to the multiplexer is Cin. A select signal is input to the multiplexer to select either Cin or XORout to be provided at the output of the multiplexer. If XORout is selected, the XOR gate operates in a first mode in which it functions as a normal XOR gate. If Cin is selected, the XOR gate operates in a second mode in which the XOR gate uses less power than when the XOR gate operates normally.

摘要翻译： 通过减少不影响逻辑输出的逻辑门进行的不必要的转换次数来减少逻辑门的某些组合的功耗的系统和方法。 在一个实施例中，修改的异或（XOR）门耦合到修改的多路复用器。 XOR门具有两个输入，即中的和B _{中的A 和作为多路复用器的输入提供的输出XOR < 。 复用器的另一个输入是中的C 。 选择信号被输入到多路复用器以选择要在多路复用器的输出处提供的或XOR 输出中的C 。 如果选择XOR ，则异或门以第一模式工作，其中它用作正常的异或门。 如果选择了中的C ，则异或门以第二模式工作，其中XOR门比XOR门正常工作时使用的功率更小。}

公开(公告)号：US20060120127A1

公开(公告)日：2006-06-08

申请号：US11003084

申请日：2004-12-03

申请人： Hiroaki Murakami ,  Hiromi Noro ,  Osamu Takahashi

发明人： Hiroaki Murakami ,  Hiromi Noro ,  Osamu Takahashi

IPC分类号： G11C15/00

CPC分类号： G11C15/00

摘要： Systems and methods for preventing the corruption of a CAM lookup result when a lookup in the CAM and a write to the CAM are concurrently executed. In one embodiment, a tag value is clocked into a tag latch simultaneously with a data value being clocked into a data latch. The tag value and initial CAM element values begin propagating through comparison logic. After a delay, the data value is written from the data latch to a CAM element. After the tag value and initial CAM values propagate through the comparison logic to produce comparison outputs, but before the newly written data value propagates through the comparison logic and changes the comparison outputs, the comparison outputs are latched. The comparison outputs can then be processed as if the data values in the CAM elements had not been changed by the write operation.

摘要翻译： 当CAM中的查找和对CAM的写入被同时执行时，用于防止CAM查找的损坏的系统和方法。 在一个实施例中，将标签值与被计入数据锁存器的数据值同时定时到标签锁存器中。 标签值和初始CAM元素值通过比较逻辑开始传播。 在延迟之后，将数据值从数据锁存器写入CAM元件。 在标签值和初始CAM值通过比较逻辑传播以产生比较输出之后，但在新写入的数据值通过比较逻辑传播并更改比较输出之前，比较输出被锁存。 然后可以像比较输出那样处理，因为CAM元素中的数据值没有被写入操作改变。

公开(公告)号：US07218152B2

公开(公告)日：2007-05-15

申请号：US11033612

申请日：2005-01-12

申请人： Hiroaki Murakami ,  Osamu Takahashi ,  Shoji Onishi

发明人： Hiroaki Murakami ,  Osamu Takahashi ,  Shoji Onishi

IPC分类号： H03K19/20

CPC分类号： H03K19/1737

摘要： Systems and methods for reducing the power consumption associated with the capacitance of sections of a multiplexer are disclosed. At each cycle, a timing signal is selectively sent only to sections of the multiplexer that include active logic. A plurality of control signals is received for processing by a corresponding plurality of input selection circuits. A plurality of additional inputs corresponding to the plurality of input selection circuits may also be received. In one embodiment, each input selection circuit is configured to output a corresponding input signal if a corresponding control signal is asserted and a timing signal is made available to the input selection circuit. To avoid unnecessary power consumption associated with the capacitance of various portions of the multiplexer, the timing signal is only asserted to a portion of the multiplexer at any given clock cycle according to the values of the control signals.

摘要翻译： 公开了用于降低与多路复用器的部分的电容相关联的功耗的系统和方法。 在每个周期，定时信号仅选择性地仅发送到包括有效逻辑的多路复用器的部分。 多个控制信号被接收用于由相应的多个输入选择电路进行处理。 还可以接收对应于多个输入选择电路的多个附加输入。 在一个实施例中，每个输入选择电路被配置为如果相应的控制信号被断言并且使定时信号对输入选择电路可用，则输出相应的输入信号。 为了避免与多路复用器的各个部分的电容相关联的不必要的功率消耗，定时信号仅根据控制信号的值以任何给定的时钟周期被认定到多路复用器的一部分。

公开(公告)号：US20060101364A1

公开(公告)日：2006-05-11

申请号：US10965625

申请日：2004-10-14

申请人： Sang Dhong ,  Hiroaki Murakami ,  Shohji Onishi ,  Osamu Takahashi

发明人： Sang Dhong ,  Hiroaki Murakami ,  Shohji Onishi ,  Osamu Takahashi

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F9/30141

摘要： A method, an apparatus, and a computer program are provided for distributing data in a high speed processing unit. Traditionally, true readout data from multiport register files are inverted multiple times when transmitting the readout to data latches, located at multiple physical layers. The inversion of the readout data can be boost the signals and provide the proper true or complement data to the data latches. To reduce the number of inverters, the register files are configured to output true and complement signals. Therefore, power consumption and area are reduced with the elimination of the inverters.

摘要翻译： 提供了一种用于在高速处理单元中分配数据的方法，装置和计算机程序。 传统上，当将多个端口寄存器文件的真实读出数据发送到位于多个物理层的数据锁存器时，会反复多次。 读出数据的反转可以提升信号，并为数据锁存器提供适当的真实或补充数据。 为了减少逆变器的数量，寄存器文件被配置为输出真实和补码信号。 因此，随着逆变器的消除，功耗和面积减少。

公开(公告)号：US07113443B2

公开(公告)日：2006-09-26

申请号：US10965627

申请日：2004-10-14

申请人： Sang Hoo Dhong ,  Hiroaki Murakami ,  Shohji Onishi ,  Osamu Takahashi

发明人： Sang Hoo Dhong ,  Hiroaki Murakami ,  Shohji Onishi ,  Osamu Takahashi

IPC分类号： G11C8/00

CPC分类号： G11C8/06

摘要： An apparatus, a method, and a computer program product are provided for time reduction and energy conservation during address distribution in a high speed memory macro. To address these concerns, this design divides the typical data arrays into sets of paired subarrays, divides the conventional memory address latches into separate sets, and interposes one set of memory address latches between each pair of subarrays. Therefore, time is saved because the address signals have less wire length to travel and energy is saved because only one set of address latches needs to be powered on for each transmission.

摘要翻译： 提供了一种在高速存储器宏中的地址分配期间用于时间减少和节能的装置，方法和计算机程序产品。 为了解决这些问题，该设计将典型的数据阵列划分为成对的阵列集合，将传统的存储器地址锁存器分成单独的集合，并在每对子阵列之间插入一组存储器地址锁存器。 因此，节省时间是因为地址信号具有更少的导线长度以保持行驶并且能量被节省，因为每个传输只需要为一个地址锁存器供电。

公开(公告)号：US20060083101A1

公开(公告)日：2006-04-20

申请号：US10965627

申请日：2004-10-14

申请人： Sang Dhong ,  Hiroaki Murakami ,  Shohji Onishi ,  Osamu Takahashi

发明人： Sang Dhong ,  Hiroaki Murakami ,  Shohji Onishi ,  Osamu Takahashi

IPC分类号： G11C8/00

CPC分类号： G11C8/06

摘要： An apparatus, a method, and a computer program product are provided for time reduction and energy conservation during address distribution in a high speed memory macro. To address these concerns, this design divides the typical data arrays into sets of paired subarrays, divides the conventional memory address latches into separate sets, and interposes one set of memory address latches between each pair of subarrays. Therefore, time is saved because the address signals have less wire length to travel and energy is saved because only one set of address latches needs to be powered on for each transmission.

公开(公告)号：US06963227B2

公开(公告)日：2005-11-08

申请号：US10295424

申请日：2002-11-15

申请人： Hiroaki Murakami ,  Shoji Onishi ,  Osamu Takahashi

发明人： Hiroaki Murakami ,  Shoji Onishi ,  Osamu Takahashi

IPC分类号： H03K19/0944 ,  H03K19/096 ,  H03K19/094

CPC分类号： H03K19/096

摘要： A domino circuit configuration includes a precharge transistor coupled to a discharge transistor, wherein the precharge transistor and the discharge transistor are not on simultaneously.

摘要翻译： 多米诺骨牌电路配置包括耦合到放电晶体管的预充电晶体管，其中预充电晶体管和放电晶体管不同时接通。

公开(公告)号：US07085147B2

公开(公告)日：2006-08-01

申请号：US11003084

申请日：2004-12-03

申请人： Hiroaki Murakami ,  Hiromi Noro ,  Osamu Takahashi

发明人： Hiroaki Murakami ,  Hiromi Noro ,  Osamu Takahashi

IPC分类号： G11C15/00

CPC分类号： G11C15/00

摘要： Systems and methods for preventing the corruption of a CAM lookup result when a lookup in the CAM and a write to the CAM are concurrently executed. In one embodiment, a tag value is clocked into a tag latch simultaneously with a data value being clocked into a data latch. The tag value and initial CAM element values begin propagating through comparison logic. After a delay, the data value is written from the data latch to a CAM element. After the tag value and initial CAM values propagate through the comparison logic to produce comparison outputs, but before the newly written data value propagates through the comparison logic and changes the comparison outputs, the comparison outputs are latched. The comparison outputs can then be processed as if the data values in the CAM elements had not been changed by the write operation.

摘要翻译： 当CAM中的查找和对CAM的写入被同时执行时，用于防止CAM查找的损坏的系统和方法。 在一个实施例中，将标签值与被计入数据锁存器的数据值同时定时到标签锁存器中。 标签值和初始CAM元素值通过比较逻辑开始传播。 在延迟之后，将数据值从数据锁存器写入CAM元件。 在标签值和初始CAM值通过比较逻辑传播以产生比较输出之后，但在新写入的数据值通过比较逻辑传播并更改比较输出之前，比较输出被锁存。 然后可以像比较输出那样处理，因为CAM元素中的数据值没有被写入操作改变。

公开(公告)号：US20060152247A1

公开(公告)日：2006-07-13

申请号：US11033612

申请日：2005-01-12

申请人： Hiroaki Murakami ,  Osamu Takahashi ,  Shoji Onishi

发明人： Hiroaki Murakami ,  Osamu Takahashi ,  Shoji Onishi

IPC分类号： H03K19/173

CPC分类号： H03K19/1737

摘要： Systems and methods for reducing the power consumption associated with the capacitance of sections of a multiplexer are disclosed. At each cycle, a timing signal is selectively sent only to sections of the multiplexer that include active logic. A plurality of control signals is received for processing by a corresponding plurality of input selection circuits. A plurality of additional inputs corresponding to the plurality of input selection circuits may also be received. In one embodiment, each input selection circuit is configured to output a corresponding input signal if a corresponding control signal is asserted and a timing signal is made available to the input selection circuit. To avoid unnecessary power consumption associated with the capacitance of various portions of the multiplexer, the timing signal is only asserted to a portion of the multiplexer at any given clock cycle according to the values of the control signals.

摘要翻译： 公开了用于降低与多路复用器的部分的电容相关联的功耗的系统和方法。 在每个周期，定时信号仅选择性地仅发送到包括有效逻辑的多路复用器的部分。 多个控制信号被接收用于由相应的多个输入选择电路进行处理。 还可以接收对应于多个输入选择电路的多个附加输入。 在一个实施例中，每个输入选择电路被配置为如果相应的控制信号被断言并且使定时信号对输入选择电路可用，则输出相应的输入信号。 为了避免与多路复用器的各个部分的电容相关联的不必要的功率消耗，定时信号仅根据控制信号的值以任何给定的时钟周期被认定到多路复用器的一部分。