- 专利标题: System for reduced power consumption by phase locked loop and method thereof
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申请号: US10083903申请日: 2002-02-27
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公开(公告)号: US07036032B2公开(公告)日: 2006-04-25
- 发明人: Carl Mizuyabu , Ken Ka Kit Kwong , Milivoje Aleksic
- 申请人: Carl Mizuyabu , Ken Ka Kit Kwong , Milivoje Aleksic
- 申请人地址: CA Thornhill
- 专利权人: ATI Technologies, Inc.
- 当前专利权人: ATI Technologies, Inc.
- 当前专利权人地址: CA Thornhill
- 主分类号: G06F1/32
- IPC分类号: G06F1/32
摘要:
A system and method are provided for reducing power consumption within a video processing portion of a system. Activity associated within a video-processing portion of a personal digital assistant is analyzed. As reduced activity is identified, power conservation modes are implemented. In a normal mode of operation, a clock signal generated through an external oscillator is provided to a phase locked loop (PLL). An output clock signal from the PLL is then provided to several dividers to generate system clock signals. In a reduced mode of operation, the output clock from the external oscillator is provided to a divider, bypassing the PLL. Video processing components then use clock signals based on the external oscillator. In a suspend mode, both the PLL and the external oscillator are disabled.
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