发明授权
US07036056B2 Semiconductor memory device having time reduced in testing of memory cell data reading or writing, or testing of sense amplifier performance
失效
半导体存储器件在存储单元数据读取或写入的测试或者读出放大器性能的测试中具有时间减少
- 专利标题： Semiconductor memory device having time reduced in testing of memory cell data reading or writing, or testing of sense amplifier performance
- 专利标题（中）： 半导体存储器件在存储单元数据读取或写入的测试或者读出放大器性能的测试中具有时间减少
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申请号： US10342396申请日： 2003-01-15
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公开(公告)号： US07036056B2公开(公告)日： 2006-04-25
- 发明人: Takashi Itoh
- 申请人： Takashi Itoh
- 申请人地址： JP Tokyo
- 专利权人： Renesas Technology Corp.
- 当前专利权人： Renesas Technology Corp.
- 当前专利权人地址： JP Tokyo
- 代理机构： McDermott Will & Emery LLP
- 优先权： JP2002-232853 20020809
- 主分类号： G11C29/00
- IPC分类号： G11C29/00
摘要：
In a read out mode, a NAND circuit to which latch data of both bit lines are input provides an L output when potentials of the bit line pair are constantly identical, and provides an H output when the potentials of the bit line pair change, even when the word line rendered active is switched. In a writing mode, the NAND circuit provides an L output. In a reading mode, H is applied to the gate of a first transistor that connects a bit line BL with the NAND circuit. In a writing mode, H is applied to the gate of the first transistor or a second transistor that connects a bit line /BL with the NAND circuit. Potential change occurs at the bit line pair according to an output of the NAND circuit.
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