- 专利标题: Method and apparatus for scalable interconnect solution
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申请号: US10071862申请日: 2002-02-07
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公开(公告)号: US07036101B2公开(公告)日: 2006-04-25
- 发明人: Limin He , So-Zen Yao , Wenyong Deng , Jing Chen , Liang-Jih Chao
- 申请人: Limin He , So-Zen Yao , Wenyong Deng , Jing Chen , Liang-Jih Chao
- 申请人地址: US CA San Jose
- 专利权人: Cadence Design Systems, Inc.
- 当前专利权人: Cadence Design Systems, Inc.
- 当前专利权人地址: US CA San Jose
- 代理机构: Blakely Sokoloff Taylor & Zafman LLP
- 主分类号: G06F9/45
- IPC分类号: G06F9/45 ; G06F17/50
摘要:
An innovative routing method for an integrated circuit design layout. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
公开/授权文献
- US20020120912A1 Method and apparatus for scalable interconnect solution 公开/授权日:2002-08-29