发明授权
US07039790B1 Very long instruction word microprocessor with execution packet spanning two or more fetch packets with pre-dispatch instruction selection from two latches according to instruction bit
有权
非常长的指令字微处理器，执行数据包跨越两个或更多个取指数据包，根据指令位从两个锁存器中进行预调度指令选择
- 专利标题： Very long instruction word microprocessor with execution packet spanning two or more fetch packets with pre-dispatch instruction selection from two latches according to instruction bit
- 专利标题（中）： 非常长的指令字微处理器，执行数据包跨越两个或更多个取指数据包，根据指令位从两个锁存器中进行预调度指令选择
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申请号： US09702320申请日： 2000-10-31
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公开(公告)号： US07039790B1公开(公告)日： 2006-05-02
- 发明人: Laurence R. Simar, Jr. , Richard A. Brown
- 申请人： Laurence R. Simar, Jr. , Richard A. Brown
- 申请人地址： US TX Dallas
- 专利权人： Texas Instruments Incorporated
- 当前专利权人： Texas Instruments Incorporated
- 当前专利权人地址： US TX Dallas
- 代理商 Robert D. Marshall, Jr.; W. James Brady, III; Frederick J. Telecky, Jr.
- 主分类号： G06F9/38
- IPC分类号： G06F9/38
摘要：
A data processing system with a microprocessor. The microprocessor has an instruction execution pipeline including fetch and decode stages and several functional execution units. Fetch packets contain a plurality of instruction words. Execute packets include a plurality of instruction words that can be executed in parallel by two or more execution units. An execution packet can span two or more fetch packets. A predetermined bit in each instruction marks whether the next instruction is executed in parallel with the current instruction. Instructions in an execute packet are dispatched to appropriate functional execution units based on instruction type. Upon a branch into an execute packet instructions at memory addresses before the branch location are not executed in parallel with instructions following the branch location.
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