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1.发明授权Very long instruction word microprocessor with execution packet spanning two or more fetch packets with pre-dispatch instruction selection from two latches according to instruction bit 有权非常长的指令字微处理器，执行数据包跨越两个或更多个取指数据包，根据指令位从两个锁存器中进行预调度指令选择公开(公告)号：US07039790B1
公开(公告)日：2006-05-02
申请号：US09702320
申请日：2000-10-31
IPC分类号： G06F9/38
CPC分类号： G06F9/3853 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3816 , G06F9/3824 , G06F9/3828 , G06F9/3885
摘要： A data processing system with a microprocessor. The microprocessor has an instruction execution pipeline including fetch and decode stages and several functional execution units. Fetch packets contain a plurality of instruction words. Execute packets include a plurality of instruction words that can be executed in parallel by two or more execution units. An execution packet can span two or more fetch packets. A predetermined bit in each instruction marks whether the next instruction is executed in parallel with the current instruction. Instructions in an execute packet are dispatched to appropriate functional execution units based on instruction type. Upon a branch into an execute packet instructions at memory addresses before the branch location are not executed in parallel with instructions following the branch location.
摘要翻译： 具有微处理器的数据处理系统。 微处理器具有指令执行流水线，其中包括读取和解码级以及若干功能执行单元。 获取分组包含多个指令字。 执行分组包括可由两个或多个执行单元并行执行的多个指令字。 执行分组可以跨越两个或更多个获取分组。 每个指令中的预定位标记下一条指令是否与当前指令并行执行。 执行数据包中的指令根据指令类型调度到适当的功能执行单元。 在分支位置不与执行分支位置之后的指令并行执行之前，在分支进入存储器地址的执行分组指令。
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公开(公告)号：US5841379A
公开(公告)日：1998-11-24
申请号：US788751
申请日：1997-01-24
IPC分类号： H03M7/46
CPC分类号： H03M7/46
摘要： A method for compression of digital data in a computer having a processor and a memory, wherein a group of consecutive bits having the same binary value is represented by a result number corresponding to the number of the consecutive bits. The method involves the following steps. A block of digital data to be compressed is provided. A bit detect selection parameter determines a bit value to be counted for counting consecutive bits. The processor is instructed to count from a first end of the block of digital data toward a second end of the block of digital data the number of consecutive bits having the bit value determined by the bit detect selection parameter. The number of bits so counted is stored, and the bit detect selection parameter is toggled. The processor is then instructed to count from the last bit counted toward the second end of the block of digital data the number of bits having the bit value determined by the current bit detect selection parameter. The foregoing steps are repeated, with successive numbers being stored representing the number of bits counted in successive counts as successive stored result numbers, until all bits in the block of digital data are counted.
摘要翻译： 一种用于在具有处理器和存储器的计算机中压缩数字数据的方法，其中具有相同二进制值的一组连续位由对应于连续位数的结果编号表示。 该方法包括以下步骤。 提供要压缩的数字数据块。 位检测选择参数确定要计数连续位的位值。 指示处理器从数字数据块的第一端向数字数据块的第二端计数具有由位检测选择参数确定的位值的连续位的数目。 存储如此计数的位数，并且切换位检测选择参数。 然后指示处理器从由数字数据块的第二端计数的最后位计数具有由当前位检测选择参数确定的位值的位数。 重复上述步骤，连续的数字被存储，表示以连续计数计数的位数作为连续存储的结果编号，直到对数字数据块中的所有位进行计数。
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3.发明授权Microprocessor with a nestable delayed branch instruction without branch related pipeline interlocks 失效具有可分支延迟分支指令的微处理器，无分支相关管道互锁
公开(公告)号：US6055628A
公开(公告)日：2000-04-25
申请号：US12676
申请日：1998-01-23
CPC分类号： G06F9/325 , G06F9/3842 , G06F9/3853
摘要： A microprocessor 1 has an instruction fetch/decode unit 10a-c, a plurality of execution units, including an arithmetic and load/store unit D1, a multiplier M1, an ALU/shifter unit S1, an arithmetic logic unit ("ALU") L1, a shared multiport register file 20a from which data are read and to which data are written, and a memory 22. These units form an instruction execution pipeline that operates without interlocks so that nestable delayed branch instructions are provided. The control circuitry for the instruction execution pipeline is operable to begin processing a second branch instruction having a second target address on a pipeline phase immediately after beginning processing of a first branch instruction having a first target address. Furthermore, the control circuitry has no interlock or delay circuitry to condition processing of the second branch instruction based on processing of the first branch instruction, therefore the program counter circuitry receives the second target address on a pipeline phase immediately after receiving the first target address regardless of whether the first branch is taken or not. Thus, one instruction may be executed from the first target branch address and then the execution sequence can be preempted to the second target address.
摘要翻译： 微处理器1具有指令提取/解码单元10a-c，多个执行单元，包括算术和加载/存储单元D1，乘法器M1，ALU /移位单元S1，算术逻辑单元（“ALU”） L1，从中读取数据并写入数据的共享多端口寄存器文件20a和存储器22.这些单元形成无互锁操作的指令执行流水线，从而提供可嵌套的延迟分支指令。 用于指令执行流水线的控制电路可操作以在开始处理具有第一目标地址的第一分支指令之后立即开始处理在流水线相位上具有第二目标地址的第二分支指令。 此外，控制电路没有互锁或延迟电路，以基于第一分支指令的处理来调节第二分支指令的处理，因此程序计数器电路在接收到第一目标地址之后立即在流水线阶段上接收第二目标地址 是否采取第一个分支。 因此，可以从第一目标分支地址执行一个指令，然后执行序列可以被抢占到第二目标地址。
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公开(公告)号：US5511146A
公开(公告)日：1996-04-23
申请号：US259373
申请日：1994-06-14
CPC分类号： G06N3/004
摘要： A set of three cellular automata--the E-Cell, the I-Cell, and the D-Node--can be used to design and assemble parallel processing networks for such applications as signal processing and artificial intelligence. The E-Cell (FIG. 1a) is an excitory cell. The I-Cell (FIG. 2a) is an inhibitory cell. The D-Node (FIG. 3) is a combination of E-Cells and I-Cells. The use of the cellular automata is illustrated in three exemplary applications: a lateral inhibition network (FIG. 5b), a tree-search network (FIG. 6b), and a graph-search network (FIG. 7e). In particular, the tree-search and graph-search networks are implemented using the same structure as the tree or graph.
摘要翻译： 一组三个细胞自动机（E-Cell，I-Cell和D-Node）可用于设计和组合用于信号处理和人工智能等应用的并行处理网络。 E细胞（图1a）是一个排泄细胞。 I细胞（图2a）是抑制细胞。 D节点（图3）是E细胞和I细胞的组合。 在三个示例性应用中示出了细胞自动机的使用：横向禁止网络（图5b），树形搜索网络（图6b）和图形搜索网络（图7e）。 特别地，树搜索和图形搜索网络使用与树或图形相同的结构来实现。
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公开(公告)号：US06374346B1
公开(公告)日：2002-04-16
申请号：US09012326
申请日：1998-01-23
IPC分类号： G06F9302
CPC分类号： G06F9/30094 , G06F9/30101 , G06F9/3842
摘要： A general purpose microprocessor architecture enabling more efficient computations of a type in which Boolean operations and arithmetic operations conditioned on the results of the Boolean operations are interleaved. The microprocessor is provided with a plurality of general purpose registers (“GPRs” 102)and an arithmetic logic unit (“ALU” 104), capable of performing arithmetic operations and Boolean operations. The ALU has a first input (108) and a second input (110), and an output (112), the first and second inputs receiving values stored in the GPRs. The output stores the results of the arithmetic logic unit operations in the GPRs. At least one of the GPRs is capable of receiving directly from the ALU a result of a Boolean operation. In one embodiment, at least one of the GPRs (PN)capable of receiving directly from the ALU a result of a Boolean operation is configured so as to cause the conditioning of an arithmetic operation of the ALU based on the value stored in the GPR.
摘要翻译： 一种通用的微处理器架构，能够更有效地计算一种类型，其中布尔运算和运算布置运算结果的算术运算被交错。 微处理器具有能够执行算术运算和布尔运算的多个通用寄存器（“GPR”102）和算术逻辑单元（“ALU”104）“。 ALU具有第一输入（108）和第二输入（110）以及输出（112），第一和第二输入接收存储在GPR中的值。 输出将算术逻辑单元操作的结果存储在GPR中。 至少有一个GPR能够直接从ALU接收布尔运算的结果。 在一个实施例中，能够直接从ALU接收到布尔运算结果的至少一个GPR（PN）被配置成基于存储在GPR中的值来调节ALU的算术运算。
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公开(公告)号：US06182203B2
公开(公告)日：2001-01-30
申请号：US09012813
申请日：1998-01-23
IPC分类号： G06F938
CPC分类号： G06F9/3891 , G06F9/30036 , G06F9/30072 , G06F9/30112 , G06F9/3012 , G06F9/30145 , G06F9/30167 , G06F9/3552 , G06F9/3824 , G06F9/3828 , G06F9/3853 , G06F9/3885 , G06F15/7857
摘要： A microprocessor, comprising a first set of functional units capable of performing parallel data operations, a second set of functional units capable of performing parallel data operations, and a data interconnection path connecting the first and second functional units.
摘要翻译： 一种微处理器，包括能够执行并行数据操作的第一组功能单元，能够执行并行数据操作的第二组功能单元，以及连接第一和第二功能单元的数据互连路径。
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