- 专利标题： Non-volatile semiconductor memory device with multi-layer gate structure
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申请号： US11020314申请日： 2004-12-27
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公开(公告)号： US07045423B2公开(公告)日： 2006-05-16
- 发明人: Masayuki Ichige , Yuji Takeuchi , Michiharu Matsui , Atsuhiro Sato , Kikuko Sugimae , Riichiro Shirota
- 申请人： Masayuki Ichige , Yuji Takeuchi , Michiharu Matsui , Atsuhiro Sato , Kikuko Sugimae , Riichiro Shirota
- 申请人地址： JP Tokyo
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JP Tokyo
- 代理机构： Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
- 优先权： JP2001-158066 20010528; JP2001-201366 20010702; JP2002-143481 20020517; JP2002-150853 20020524
- 主分类号： H01L21/8247
- IPC分类号： H01L21/8247
摘要：
A semiconductor device includes a semiconductor substrate, source and drain regions, a channel region, a gate insulating film, a charge storage layer, and a control gate electrode. The source and drain regions include first impurities of a first conductivity type. The channel region includes second impurities of a second conductivity type. The gate insulating film includes the second impurities in a region thereof located immediately above at least a portion of the channel region. The charge storage layer is formed on the gate insulating film. The control gate electrode is provided on the charge storage layer. The control gate electrode is formed on the charge storage layer and is electrically connected to the charge storage layer by a connection portion provided on a part of the charge storage layer, which is located immediately above at least a part of the region of the gate insulating film including the second impurities.