公开(公告)号：US06853029B2

公开(公告)日：2005-02-08

申请号：US10155086

申请日：2002-05-28

申请人： Masayuki Ichige ,  Yuji Takeuchi ,  Michiharu Matsui ,  Atsuhiro Sato ,  Kikuko Sugimae ,  Riichiro Shirota

发明人： Masayuki Ichige ,  Yuji Takeuchi ,  Michiharu Matsui ,  Atsuhiro Sato ,  Kikuko Sugimae ,  Riichiro Shirota

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor device includes a semiconductor substrate, source and drain regions, a channel region, a gate insulating film, a charge storage layer, and a control gate electrode. The source and drain regions include first impurities of a first conductivity type. The channel region includes second impurities of a second conductivity type. The gate insulating film includes the second impurities in a region thereof located immediately above at least a portion of the channel region. The charge storage layer is formed on the gate insulating film. The control gate electrode is provided on the charge storage layer. The control gate electrode is formed on the charge storage layer and is electrically connected to the charge storage layer by a connection portion provided on a part of the charge storage layer, which is located immediately above at least a part of the region of the gate insulating film including the second impurities.

摘要翻译： 半导体器件包括半导体衬底，源极和漏极区，沟道区，栅极绝缘膜，电荷存储层和控制栅电极。 源区和漏区包括第一导电类型的第一杂质。 沟道区域包括第二导电类型的第二杂质。 栅极绝缘膜包括位于沟道区域的至少一部分正上方的区域中的第二杂质。 电荷存储层形成在栅极绝缘膜上。 控制栅电极设置在电荷存储层上。 控制栅电极形成在电荷存储层上，并且通过设置在电荷存储层的一部分上的连接部分电连接到电荷存储层，所述连接部位于栅极绝缘区域的至少一部分的正上方 膜包括第二杂质。

公开(公告)号：US07045423B2

公开(公告)日：2006-05-16

申请号：US11020314

申请日：2004-12-27

申请人： Masayuki Ichige ,  Yuji Takeuchi ,  Michiharu Matsui ,  Atsuhiro Sato ,  Kikuko Sugimae ,  Riichiro Shirota

发明人： Masayuki Ichige ,  Yuji Takeuchi ,  Michiharu Matsui ,  Atsuhiro Sato ,  Kikuko Sugimae ,  Riichiro Shirota

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor device includes a semiconductor substrate, source and drain regions, a channel region, a gate insulating film, a charge storage layer, and a control gate electrode. The source and drain regions include first impurities of a first conductivity type. The channel region includes second impurities of a second conductivity type. The gate insulating film includes the second impurities in a region thereof located immediately above at least a portion of the channel region. The charge storage layer is formed on the gate insulating film. The control gate electrode is provided on the charge storage layer. The control gate electrode is formed on the charge storage layer and is electrically connected to the charge storage layer by a connection portion provided on a part of the charge storage layer, which is located immediately above at least a part of the region of the gate insulating film including the second impurities.

公开(公告)号：US20050104120A1

公开(公告)日：2005-05-19

申请号：US11020314

申请日：2004-12-27

申请人： Masayuki Ichige ,  Yuji Takeuchi ,  Michiharu Matsui ,  Atsuhiro Sato ,  Kikuko Sugimae ,  Riichiro Shirota

发明人： Masayuki Ichige ,  Yuji Takeuchi ,  Michiharu Matsui ,  Atsuhiro Sato ,  Kikuko Sugimae ,  Riichiro Shirota

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/15 ,  H01L21/82

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor device includes a semiconductor substrate, source and drain regions, a channel region, a gate insulating film, a charge storage layer, and a control gate electrode. The source and drain regions include first impurities of a first conductivity type. The channel region includes second impurities of a second conductivity type. The gate insulating film includes the second impurities in a region thereof located immediately above at least a portion of the channel region. The charge storage layer is formed on the gate insulating film. The control gate electrode is provided on the charge storage layer. The control gate electrode is formed on the charge storage layer and is electrically connected to the charge storage layer by a connection portion provided on a part of the charge storage layer, which is located immediately above at least a part of the region of the gate insulating film including the second impurities.

公开(公告)号：US07504294B2

公开(公告)日：2009-03-17

申请号：US10881180

申请日：2004-07-01

申请人： Kikuko Sugimae ,  Hiroyuki Kutsukake ,  Masayuki Ichige ,  Michiharu Matsui ,  Yuji Takeuchi ,  Riichiro Shirota

发明人： Kikuko Sugimae ,  Hiroyuki Kutsukake ,  Masayuki Ichige ,  Michiharu Matsui ,  Yuji Takeuchi ,  Riichiro Shirota

IPC分类号： H01L21/8238

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529

摘要： A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.

摘要翻译： 半导体器件包括存储单元阵列部分和外围电路部分，其中包括作为除氮之外的主要成分的元素的第一绝缘膜填充在存储单元阵列部分的存储单元栅电极之间，第一绝缘膜形成为衬垫 在周边电路部分的外围栅电极的侧壁上与存储单元部分同时，并且通过第一绝缘膜在外围栅电极的侧壁上形成包括氮作为主要成分的第二绝缘膜，从而不能 仅形成具有高可靠性的存储单元部分，而且形成具有良好效率的周边电路，同时避免了外围栅极的栅极偏移。

公开(公告)号：US07417281B2

公开(公告)日：2008-08-26

申请号：US11733488

申请日：2007-04-10

申请人： Kikuko Sugimae ,  Hiroyuki Kutsukake ,  Masayuki Ichige ,  Michiharu Matsui ,  Yuji Takeuchi ,  Riichiro Shirota

发明人： Kikuko Sugimae ,  Hiroyuki Kutsukake ,  Masayuki Ichige ,  Michiharu Matsui ,  Yuji Takeuchi ,  Riichiro Shirota

IPC分类号： H01L29/94

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529

摘要： A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.

摘要翻译： 半导体器件包括存储单元阵列部分和外围电路部分，其中包括作为除氮之外的主要成分的元素的第一绝缘膜填充在存储单元阵列部分的存储单元栅电极之间，第一绝缘膜形成为衬垫 在周边电路部分的外围栅电极的侧壁上与存储单元部分同时，并且通过第一绝缘膜在外围栅电极的侧壁上形成包括氮作为主要成分的第二绝缘膜，从而不能 仅形成具有高可靠性的存储单元部分，而且形成具有良好效率的周边电路，同时避免了外围栅极的栅极偏移。

公开(公告)号：US20070187749A1

公开(公告)日：2007-08-16

申请号：US11733488

申请日：2007-04-10

申请人： Kikuko Sugimae ,  Hiroyuki Kutsukake ,  Masayuki Ichige ,  Michiharu Matsui ,  Yuji Takeuchi ,  Riichiro Shirota

发明人： Kikuko Sugimae ,  Hiroyuki Kutsukake ,  Masayuki Ichige ,  Michiharu Matsui ,  Yuji Takeuchi ,  Riichiro Shirota

IPC分类号： H01L29/788

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529

摘要： A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.

摘要翻译： 半导体器件包括存储单元阵列部分和外围电路部分，其中包括作为除氮之外的主要成分的元素的第一绝缘膜填充在存储单元阵列部分的存储单元栅电极之间，第一绝缘膜形成为衬垫 在周边电路部分的外围栅电极的侧壁上与存储单元部分同时，并且通过第一绝缘膜在外围栅电极的侧壁上形成包括氮作为主要成分的第二绝缘膜，从而不能 仅形成具有高可靠性的存储单元部分，而且形成具有良好效率的周边电路，同时避免了外围栅极的栅极偏移。

公开(公告)号：US06894341B2

公开(公告)日：2005-05-17

申请号：US10326179

申请日：2002-12-23

申请人： Kikuko Sugimae ,  Hiroyuki Kutsukake ,  Masayuki Ichige ,  Michiharu Matsui ,  Yuji Takeuchi ,  Riichiro Shirota

发明人： Kikuko Sugimae ,  Hiroyuki Kutsukake ,  Masayuki Ichige ,  Michiharu Matsui ,  Yuji Takeuchi ,  Riichiro Shirota

IPC分类号： H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L31/0328

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529

摘要： A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.

摘要翻译： 半导体器件包括存储单元阵列部分和外围电路部分，其中包括作为除氮之外的主要成分的元素的第一绝缘膜填充在存储单元阵列部分的存储单元栅电极之间，第一绝缘膜形成为衬垫 在周边电路部分的外围栅电极的侧壁上与存储单元部分同时，并且通过第一绝缘膜在外围栅电极的侧壁上形成包括氮作为主要成分的第二绝缘膜，从而不能 仅形成具有高可靠性的存储单元部分，而且形成具有良好效率的周边电路，同时避免了外围栅极的栅极偏移。

公开(公告)号：US06921960B2

公开(公告)日：2005-07-26

申请号：US09984718

申请日：2001-10-31

申请人： Masayuki Ichige ,  Riichiro Shirota ,  Kikuko Sugimae ,  Atsuhiro Sato ,  Yuji Takeuchi

发明人： Masayuki Ichige ,  Riichiro Shirota ,  Kikuko Sugimae ,  Atsuhiro Sato ,  Yuji Takeuchi

IPC分类号： H01L21/768 ,  H01L21/822 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/08 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/00

CPC分类号： H01L27/11526 ,  H01L27/0805 ,  H01L27/105 ,  H01L27/11531

摘要： A semiconductor device includes a structure in which a first electrode layer, an inter-electrode insulating film and a second electrode layer are laminated in a main circuit in this order, and includes a capacitor element having a lower electrode formed of the same layer as the first electrode layer, a charge storage layer formed of the same layer as the inter-electrode insulating film, and an upper electrode formed of the second electrode layer. The semiconductor device further includes an opening portion formed in the charge storage layer, the opening portion having a bottom to which the lower electrode is exposed, and a first region electrically connected to the lower electrode via the opening portion and electrically isolated from the upper electrode, the first region being formed of the same layer as the second electrode layer.

摘要翻译： 半导体器件包括其中第一电极层，电极间绝缘膜和第二电极层依次层叠在主电路中的结构，并且包括电容器元件，其具有由与第一电极层相同的层形成的下电极 第一电极层，由与电极间绝缘膜相同的层形成的电荷存储层和由第二电极层形成的上电极。 半导体装置还包括形成在电荷存储层中的开口部分，开口部分具有露出下部电极的底部，以及经由开口部分电连接到下部电极并与上部电极电隔离的第一区域 所述第一区域由与所述第二电极层相同的层形成。

公开(公告)号：US06667507B2

公开(公告)日：2003-12-23

申请号：US09899155

申请日：2001-07-06

申请人： Riichiro Shirota ,  Kikuko Sugimae ,  Masayuki Ichige ,  Atsuhiro Sato ,  Hiroaki Hazama

发明人： Riichiro Shirota ,  Kikuko Sugimae ,  Masayuki Ichige ,  Atsuhiro Sato ,  Hiroaki Hazama

IPC分类号： H01L29788

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11536

摘要： A semiconductor memory device includes a semiconductor substrate, an element isolation region formed in the semiconductor substrate and including a thick element isolating insulation film, for isolating an element region, a first gate electrode provided on the element region in the semiconductor substrate in self-alignment with the element isolation region, a second gate electrode provided on the first gate electrode with an insulation film interposed therebetween, and a resistance element formed on the element isolation region, the resistance element and the second gate electrode being formed of the same conductive film.

摘要翻译： 半导体存储器件包括半导体衬底，形成在半导体衬底中并包括用于隔离元件区的厚元件隔离绝缘膜的元件隔离区，设置在半导体衬底中的元件区域上的自对准的第一栅电极 在元件隔离区域中，设置在第一栅电极上的绝缘膜的第二栅极电极和形成在元件隔离区域上的电阻元件，电阻元件和第二栅电极由相同的导电膜形成。

公开(公告)号：US07361951B2

公开(公告)日：2008-04-22

申请号：US11259142

申请日：2005-10-27

申请人： Riichiro Shirota ,  Kikuko Sugimae ,  Masayuki Ichige ,  Atsuhiro Sato ,  Hiroaki Hazama

发明人： Riichiro Shirota ,  Kikuko Sugimae ,  Masayuki Ichige ,  Atsuhiro Sato ,  Hiroaki Hazama

IPC分类号： H01L29/788

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11536

摘要： A semiconductor memory device includes a semiconductor substrate, an element isolation region formed in the semiconductor substrate and including a thick element isolating insulation film, for isolating an element region, a first gate electrode provided on the element region in the semiconductor substrate in self-alignment with the element isolation region, a second gate electrode provided on the first gate electrode with an insulation film interposed therebetween, and a resistance element formed on the element isolation region, the resistance element and the second gate electrode being formed of the same conductive film.

摘要翻译： 半导体存储器件包括半导体衬底，形成在半导体衬底中并包括用于隔离元件区的厚元件隔离绝缘膜的元件隔离区，设置在半导体衬底中的元件区域上的自对准的第一栅电极 在元件隔离区域中，设置在第一栅电极上的绝缘膜的第二栅极电极和形成在元件隔离区域上的电阻元件，电阻元件和第二栅电极由相同的导电膜形成。