Invention Grant
- Patent Title: Semiconductor structure having a strained region and a method of fabricating same
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Application No.: US10657616Application Date: 2003-09-08
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Publication No.: US07045836B2Publication Date: 2006-05-16
- Inventor: Wen-Chin Lee , Chung-Hu Ge , Chenming Hu
- Applicant: Wen-Chin Lee , Chung-Hu Ge , Chenming Hu
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A semiconductor structure including a highly strained selective epitaxial top layer suitable for use in fabricating a strained channel transistor. The top layer is deposited on the uppermost of a series of one or more lower layers. The lattice of each layer is mismatched with the lattice of its subjacent layer by an amount not less than the lattice mismatch between the lowest layer of the series and a substrate on which it resides. A trench is formed in the uppermost series layer. The trench has rounded corners so that a dielectric material filling the trench conforms to the round corners. The rounded corners are produced by heating the uppermost series layer after trench formation.
Public/Granted literature
- US20050023576A1 Semiconductor structure having a strained region and a method of fabricating same Public/Granted day:2005-02-03
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