公开(公告)号：US08569146B2

公开(公告)日：2013-10-29

申请号：US13013296

申请日：2011-01-25

Applicant: Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chung-Hu Ge

Inventor： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chung-Hu Ge

IPC: H01L21/76

CPC classification number: H01L21/823878 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/7846 ,  H01L29/7848

Abstract: A method and system is disclosed for forming an improved isolation structure for strained channel transistors. In one example, an isolation structure is formed comprising a trench filled with a nitrogen-containing liner and a gap filler. The nitrogen-containing liner enables the isolation structure to reduce compressive strain contribution to the channel region.

Abstract translation: 公开了用于形成用于应变通道晶体管的改进的隔离结构的方法和系统。 在一个示例中，形成包括填充有含氮衬里和间隙填料的沟槽的隔离结构。 含氮衬垫使隔离结构能够减小对通道区域的压应变贡献。

公开(公告)号：US07183593B2

公开(公告)日：2007-02-27

申请号：US10745831

申请日：2003-12-24

Applicant: Yee-Chia Yeo ,  Wen-Chin Lee ,  Chih-Hsin Ko ,  Chung-Hu Ge ,  Chun-Chieh Lin ,  Chenming Hu

Inventor： Yee-Chia Yeo ,  Wen-Chin Lee ,  Chih-Hsin Ko ,  Chung-Hu Ge ,  Chun-Chieh Lin ,  Chenming Hu

IPC: H01L29/86 ,  H01L29/205

CPC classification number: H01L27/0629 ,  H01L29/165 ,  H01L29/8605

Abstract: A heterostructure resistor comprises a doped region formed in a portion of a semiconductor substrate, the substrate comprising a first semiconductor material having a first natural lattice constant. The doped region comprises a semiconductor layer overlying the semiconductor substrate. The semiconductor layer comprises a second semiconductor material with a second natural lattice constant.

Abstract translation: 异质结构电阻器包括形成在半导体衬底的一部分中的掺杂区域，该衬底包括具有第一自然晶格常数的第一半导体材料。 掺杂区域包括覆盖半导体衬底的半导体层。 半导体层包括具有第二自然晶格常数的第二半导体材料。

公开(公告)号：US06974755B2

公开(公告)日：2005-12-13

申请号：US10687377

申请日：2003-10-16

Applicant: Chih-Hsin Ko ,  Yee-Chia Yeo ,  Chung-Hu Ge ,  Wen-Chin Lee

Inventor： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Chung-Hu Ge ,  Wen-Chin Lee

IPC: H01L21/28 ,  H01L21/306 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L21/28123 ,  H01L21/76232 ,  H01L21/823481 ,  H01L29/7833

Abstract: A semiconductor isolation trench includes a substrate and a trench formed therein. The trench is lined with a nitrogen-containing liner and filled with a dielectric material. The nitrogen-containing liner preferably contacts the active region of a device, such as a transistor, located adjacent to the trench.

Abstract translation: 半导体隔离沟槽包括衬底和形成在其中的沟槽。 沟槽衬有含氮衬里并填充介电材料。 优选地，所述含氮衬垫接触位于所述沟槽附近的诸如晶体管的器件的有源区。

公开(公告)号：US20050247986A1

公开(公告)日：2005-11-10

申请号：US10840911

申请日：2004-05-06

Applicant: Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ge

Inventor： Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ge

IPC: H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/7845 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843 ,  Y10S257/90

Abstract: A strained channel transistor and method for forming the the strained channel transistor including a semiconductor rate; a gate dielectric overlying a channel region; a gate rode overlying the gate dielectric; source drain extension regions and source and drain (S/D) regions; wherein a sed dielectric portion selected from the group consisting of r of stressed offset spacers disposed adjacent the gate rode and a stressed dielectric layer disposed over the gate rode including the S/D regions is disposed to exert a strain channel region.

Abstract translation: 一种应变通道晶体管和用于形成包括半导体速率的应变通道晶体管的方法; 覆盖沟道区的栅极电介质; 栅极覆盖栅极电介质; 源极漏极延伸区域和源极和漏极（S / D）区域; 其中设置选自由围绕所述栅极环配置的应力偏移间隔的r和设置在包括所述S / D区的所述栅极周围的应力介电层的施放电介质部分以施加应变通道区域。

公开(公告)号：US20050116360A1

公开(公告)日：2005-06-02

申请号：US10896270

申请日：2004-07-21

Applicant: Chien-Chao Huang ,  Fu-Liang Yang ,  Mickey Ken ,  Chenming Hu ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chih-Hsin Ko

Inventor： Chien-Chao Huang ,  Fu-Liang Yang ,  Mickey Ken ,  Chenming Hu ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chih-Hsin Ko

IPC: H01L21/336 ,  H01L21/76 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L31/0328

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/045 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845

Abstract: A complementary FET and a method of manufacture is provided. The complementary FET utilizes a substrate having a surface layer with a crystal orientation. Tensile stress, which increases performance of the NMOS FETs, is added by silicided source/drain regions, tensile-stress film, shallow trench isolations, inter-layer dielectric, or the like.

Abstract translation: 提供互补的FET和制造方法。 互补FET使用具有<100>晶体取向的表面层的衬底。 通过硅化源极/漏极区域，拉伸应力膜，浅沟槽隔离层，层间电介质等添加了提高NMOS FET的性能的拉伸应力。

公开(公告)号：US20050093018A1

公开(公告)日：2005-05-05

申请号：US10699574

申请日：2003-10-31

Applicant: Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu

Inventor： Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/338 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/10 ,  H01L29/74 ,  H01L29/78 ,  H01L31/0328 ,  H01L31/072

CPC classification number: H01L29/0847 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842

Abstract: A semiconductor device includes a substrate, a first epitaxial layer, a second epitaxial layer, a third epitaxial layer, a first trench, and a second trench. The first epitaxial layer is formed on the substrate. The first layer has lattice mismatch relative to the substrate. The second epitaxial layer is formed on the first layer, and the second layer has lattice mismatch relative to the first layer. The third epitaxial layer is formed on the second layer, and the third layer has lattice mismatch relative to the second layer. Hence, the third layer may be strained silicon. The first trench extends through the first layer. The second trench extends through the third layer and at least partially through the second layer. At least part of the second trench is aligned with at least part of the first trench, and the second trench is at least partially filled with an insulating material.

Abstract translation: 半导体器件包括衬底，第一外延层，第二外延层，第三外延层，第一沟槽和第二沟槽。 第一外延层形成在基板上。 第一层相对于衬底具有晶格失配。 第二外延层形成在第一层上，第二层相对于第一层具有晶格失配。 第三外延层形成在第二层上，第三层相对于第二层具有晶格失配。 因此，第三层可以是应变硅。 第一沟槽延伸穿过第一层。 第二沟槽延伸穿过第三层并且至少部分地穿过第二层。 所述第二沟槽的至少一部分与所述第一沟槽的至少一部分对准，并且所述第二沟槽至少部分地填充有绝缘材料。

公开(公告)号：US20050045969A1

公开(公告)日：2005-03-03

申请号：US10880992

申请日：2004-06-30

Applicant: Wen-Chin Lee ,  Chung-Hu Ge ,  Chenming Hu

Inventor： Wen-Chin Lee ,  Chung-Hu Ge ,  Chenming Hu

IPC: H01L21/336 ,  H01L23/31 ,  H01L23/485 ,  H01L23/62 ,  H01L27/088 ,  H01L27/105 ,  H01L29/161 ,  H01L29/165 ,  H01L29/47 ,  H01L29/78

CPC classification number: H01L23/3192 ,  H01L23/485 ,  H01L29/161 ,  H01L29/165 ,  H01L29/47 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7834 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A preferred embodiment of the present invention comprises a dielectric/metal/2nd energy bandgap (Eg) semiconductor/1st Eg substrate structure. In order to reduce the contact resistance, a semiconductor with a lower energy bandgap (2nd Eg) is put in contact with metal. The energy bandgap of the 2nd Eg semiconductor is lower than the energy bandgap of the 1st Eg semiconductor and preferably lower than 1.1 eV. In addition, a layer of dielectric may be deposited on the metal. The dielectric layer has built-in stress to compensate for the stress in the metal, 2nd Eg semiconductor and 1st Eg substrate. A process of making the structure is also disclosed.

Abstract translation: 本发明的优选实施例包括介电/金属/第二能带隙（Eg）半导体/第一基板结构。 为了降低接触电阻，将具有较低能带隙（2Egg）的半导体与金属接触。 第二半导体元件的能量带隙低于第一半导体器件的能带隙，优选低于1.1eV。 此外，可以在金属上沉积介电层。 电介质层具有内置的应力，以补偿金属，第二半导体和第一基板中的应力。 还公开了制造该结构的过程。

公开(公告)号：US07029994B2

公开(公告)日：2006-04-18

申请号：US11083537

申请日：2005-03-18

Applicant: Chung-Hu Ge ,  Chao-Hsiung Wang ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Chenming Hu

Inventor： Chung-Hu Ge ,  Chao-Hsiung Wang ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Chenming Hu

IPC: H01L21/20

CPC classification number: H01L21/823807 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7848

Abstract: A semiconductor device 10 includes a substrate 12 (e.g., a silicon substrate) with an insulating layer 14 (e.g., an oxide such as silicon dioxide) disposed thereon. A first semiconducting material layer 16 (e.g., SiGe) is disposed on the insulating layer 14 and a second semiconducting material layer 18 (e.g., Si) is disposed on the first semiconducting material layer 16. The first and second semiconducting material layers 16 and 18 preferably have different lattice constants such that the first semiconducting material layer 16 is compressive and the second semiconducting material layer is tensile 18.

Abstract translation: 半导体器件10包括其上设置有绝缘层14（例如氧化物如二氧化硅）的衬底12（例如，硅衬底）。 第一半导体材料层16（例如，SiGe）设置在绝缘层14上，并且第二半导体材料层18（例如，Si）设置在第一半导体材料层16上。 第一和第二半导体材料层16和18优选地具有不同的晶格常数，使得第一半导体材料层16是压缩的，并且第二半导体材料层是拉伸18。

公开(公告)号：US06924181B2

公开(公告)日：2005-08-02

申请号：US10366220

申请日：2003-02-13

Applicant: Chien-Chao Huang ,  Chao-Hsiung Wang ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chen Ming Hu

Inventor： Chien-Chao Huang ,  Chao-Hsiung Wang ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chen Ming Hu

IPC: H01L21/28 ,  H01L29/778 ,  H01L21/336

CPC classification number: H01L29/7842 ,  H01L21/2807 ,  H01L29/7782 ,  Y10S438/933

Abstract: A strained silicon layer fabrication and a method for fabrication thereof employ a strained insulator material layer formed over a strained silicon layer in turn formed upon a strained silicon-germanium alloy material layer which is formed upon a relaxed material substrate. The strained insulator material layer provides increased fabrication options which provide for enhanced fabrication efficiency when fabricating the strained silicon layer fabrication.

Abstract translation: 应变硅层制造及其制造方法采用在应变硅层上形成的应变绝缘体材料层，其又形成在形成于松弛材料基板上的应变硅 - 锗合金材料层上。 应变绝缘体材料层提供增加的制造选择，其在制造应变硅层制造时提供增强的制造效率。

公开(公告)号：US20110117724A1

公开(公告)日：2011-05-19

申请号：US13013296

申请日：2011-01-25

Applicant: Chih-Hsin KO ,  Yee-Chia YEO ,  Wen-Chin LEE ,  Chung-Hu GE

Inventor： Chih-Hsin KO ,  Yee-Chia YEO ,  Wen-Chin LEE ,  Chung-Hu GE

IPC: H01L21/762 ,  H01L21/763

CPC classification number: H01L21/823878 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/7846 ,  H01L29/7848

Abstract: A method and system is disclosed for forming an improved isolation structure for strained channel transistors. In one example, an isolation structure is formed comprising a trench filled with a nitrogen-containing liner and a gap filler. The nitrogen-containing liner enables the isolation structure to reduce compressive strain contribution to the channel region.

Abstract translation: 公开了一种用于形成用于应变通道晶体管的改进的隔离结构的方法和系统。 在一个示例中，形成包括填充有含氮衬里和间隙填料的沟槽的隔离结构。 含氮衬垫使隔离结构能够减小对通道区域的压应变贡献。