Invention Grant
- Patent Title: Area efficient waveform evaluation and DC offset cancellation circuits
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Application No.: US09896345Application Date: 2001-06-28
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Publication No.: US07049855B2Publication Date: 2006-05-23
- Inventor: Krishnamurthy Soumyanath , Luiz Franca-Neto
- Applicant: Krishnamurthy Soumyanath , Luiz Franca-Neto
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: G01R19/00
- IPC: G01R19/00

Abstract:
Analog circuits for providing one or more waveform parameters, e.g., the DC offset or average, of an analog input signal. Separate biasing is not necessarily required. Some embodiments comprise field-effect-transistors (FETs) configured in various diode-connected configurations that take advantage of leakage currents through the FETs so that long resistors or large capacitors are not necessarily required. One embodiment comprises two diode-connected FETs to provide an unbiased DC offset voltage of an analog input signal.
Public/Granted literature
- US20030001653A1 Area efficient waveform evaluation and DC offset cancellation circuits Public/Granted day:2003-01-02
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