An integrated device including a first memory array having first memory cells of a nonvolatile type and a second memory array having second memory cells of a volatile type (DRAM). The first memory cells and the second memory cells are formed in a substrate of semiconductor material, and each includes a respective MOS transistor which is formed in an active region of the substrate and has a first conductive region and a respective capacitor which is formed on top of the active region and has a first electrode and a second electrode, which are separated by a dielectric region. Moreover, the first electrode of the capacitor is connected to the first conductive region of the MOS transistor. The first and the second memory cells have a structure that is substantially the same and are formed simultaneously.