发明授权
- 专利标题: Scalable on chip network
- 专利标题(中): 可扩展的片上网络
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申请号: US10207600申请日: 2002-07-29
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公开(公告)号: US07051150B2公开(公告)日: 2006-05-23
- 发明人: Mark W. Naumann , Gary A. Walker , Ned D. Garinger , Martin L. Dorr
- 申请人: Mark W. Naumann , Gary A. Walker , Ned D. Garinger , Martin L. Dorr
- 申请人地址: US TX Austin
- 专利权人: Freescale Semiconductor, Inc.
- 当前专利权人: Freescale Semiconductor, Inc.
- 当前专利权人地址: US TX Austin
- 代理商 Gary R. Stanford
- 主分类号: G06F13/00
- IPC分类号: G06F13/00
摘要:
A scalable network for supporting an application using processing elements including ports, an interconnect, port interfaces, and an arbiter. Each port conforms to a consistent port interface protocol regardless of number of ports, frequency of operation, maximum datum width or data path concurrency. The interconnect has a scalable maximum datum width and a scalable data path concurrency, and includes selectable data paths between any two ports to enable transfer of datums between the ports. Each port interface formulates packets for transmission and receives packets via the corresponding port and the interconnect, where each packet includes one or more datums. The arbiter controls packet transfer via the interconnect between source and destination ports. The interconnect has a scalable data path concurrency. Pipeline stages may be added to support a selected clock frequency. The OCN may be a component library including bus gasket, interconnect and arbiter components.
公开/授权文献
- US20040024946A1 Scalable on chip network 公开/授权日:2004-02-05
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